BBC Master 128

A Model B rebuilt around four Acorn gate arrays and a 1 Mbit ROM; most dead Masters are a leaked battery, a lost 16 MHz clock or a confused CMOS RAM.

Open the BBC Master 128 in Retro Bench
Also
BBC Master Series
Year
1986
CPU
65SC12 (CMOS 6502 with the 65C02 extra instructions) at 2 MHz
RAM
128 KB: 4 x 4464 (64K x 4). 64 KB main (with shadow LYNNE, HAZEL, ANDY) + 64 KB sideways RAM in slots 4-7
ROM
128 KB (1 Mbit) ROM: MOS, BASIC IV, ADFS, DFS, VIEW, ViewSheet, EDIT, Terminal; IC27 16K socket, IC37/IC41 32K sockets, two cartridge slots
Video
VIDPROC + 6845 + SAA5050, as the Model B, plus shadow MODEs 128-135
Sound
SN76489 (IC12), internal speaker and a rear phono socket
OS
MOS 3 with BBC BASIC IV; battery-backed 146818 clock and CMOS configuration

Chips

ChipWhereRole
65SC12 CMOS CPUIC14Main CPU of the Master. Runs every 6502 instruction plus the 65C02 additions.
Master I/O controller gate array (CF30050)IC15Decodes SHEILA chip selects (VIDPROC, ACIA, SERPROC, ADC, FDC), drives RDY and turns FDC DRQ into NMI.
Master memory controller gate array (CF30058)IC20ROMSEL (&FE30) and ACCCON (&FE34): pages ROMs, sideways RAM, shadow LYNNE, HAZEL and ANDY.
Master peripheral bus controller (CF30049)IC21Buffers the data bus to slow I/O, the 1 MHz bus and the external Tube (EXbus).
Video ULA (Ferranti 5C094 / VLSI VC2069 VIDPROC)IC42Serializes screen bytes into RGB through a 16-entry palette, mixes in teletext, draws the cursor and divides 16 MHz into 8, 4, 2 and 1 MHz.
MC6845 CRT controllerIC22Makes sync, display enable, cursor and the video RAM refresh addresses.
Master CRTC multiplexer gate arrayIC31Turns 6845 MA/RA addresses into DRAM addresses with hardware-scroll wrap-around (C0, C1 on pins 38-39).
Mullard SAA5050 teletext character generatorIC32Teletext character generator: turns 7-bit character codes into rounded characters, colors and block graphics.
6522 VIAIC8 (system VIA), IC6 (user VIA)Two 8-bit ports, timers, serial and user port
Serial ULA (Ferranti 2C199 / VLSI VC2026 SERPROC)IC48Baud rate generators for the 6850, switching between cassette and RS423, cassette data separator, tone synthesis and motor control.
MC6850 asynchronous comms adapterIC45Asynchronous serial interface (ACIA).
SN76489 / SN94624 (TMS9919) sound generatorIC12Three tone voices and one noise voice, written over an 8-bit data bus.
MC146818A real-time clock with RAMIC11Clock, calendar, alarm and 50 bytes of battery-backed RAM.
NEC uPD7002 4-channel A/D converterIC49Four-channel integrating A/D converter, 8 or 10-bit, with a microprocessor bus interface.
WD1770 / WD1772 floppy disk controllerIC3Single and double density floppy disk controller with built-in data separator and write precompensation.
MC68B54 advanced data link controller (ADLC)Econet module (daughter board)Advanced data link controller: HDLC/SDLC framing, flag detection, CRC and FIFOs.
4464 / 41464 DRAM 64K x 4IC17, IC18, IC23, IC26Dynamic RAM, 64K x 4. Main RAM on the BBC Master; reported on later 130XE boards.
Master keyboard encoder (CF30047)IC1640-pin keyboard scanner: free-runs at 1 MHz, interrupts on CA2, then answers the OS row/column polls.
Master CHROMA (PAL/NTSC encoder) gate array (CF30060)IC40Encodes RGB to PAL (or NTSC, LK15) for the UHF modulator; can also supply the 1.23 MHz serial clock (LK14).
27128-pinout 16K x 8 ROMIC27 (16K socket, ROM 8)16K x 8 ROM or EPROM in the JEDEC 27128 pinout.

Ports and connectors

Power rails

RailExpectMeasure at
+5 V+5 V65SC12 pin 8; VIDPROC pin 16; SAA5050 pin 18; 1770 pin 15
-5 V-5 VRS423 driver 26LS30 (IC50) pin 8
Clock batteryAt least 2.6 V with mains off UNVERIFIEDRTC pin 24 (146818 VDD)
ADC referenceAbout 1.8 V7002 pin 8 to 7002 pin 9

Symptoms