Video ULA (Ferranti 5C094 / VLSI VC2069 VIDPROC) pinout

DIP-28. Serializes screen bytes into RGB through a 16-entry palette, mixes in teletext, draws the cursor and divides 16 MHz into 8, 4, 2 and 1 MHz.

All the system clocks come out of this chip, so a dead one stops the whole machine. The original Ferranti 5C094 runs hot and needs its heatsink: twinkling characters or a smeared cursor that appear after months of use usually mean the heatsink has come loose (SM 6.4). Later VLSI VIDPROC parts (VC2023 needs a patch wire, VC2069 is a direct swap; Acorn part 201,647) run cool. Registers: control at &FE20, palette at &FE21.

Open the interactive VIDPROC pinout

Pins

PinNameTypeSignal
1GNDgroundGround.
2A0addrRegister select: 0 = control (&FE20), 1 = palette (&FE21).
3/CSctrlChip select (VIDPROC decode, write only).
41MHzclock1 MHz out (Model B: used for the teletext chip).
52MHzclock2 MHz out (CPU clock source).
64MHzclock4 MHz out (DRAM timing).
78MHzclock8 MHz out (DRAM timing, disk).
816MHzclock16 MHz master clock in from the crystal oscillator (IC43 on the Model B).
9BINvideoBlue in from the SAA5050 (teletext).
10BvideoBlue out to the RGB buffers and PAL encoder.
11GINvideoGreen in from the SAA5050.
12GvideoGreen out.
13RINvideoRed in from the SAA5050.
14RvideoRed out.
15V2powerReference of about 2.2 V from D16-D18 and R114 (Model B); also biases the 16 MHz input through R107.
16V1power+5 V.
17D0dataData bit 0: screen bytes from the DRAM bus, register writes from the CPU.
18D1dataData bit 1.
19D2dataData bit 2.
20D3dataData bit 3.
21D4dataData bit 4.
22D5dataData bit 5.
23D6dataData bit 6.
24D7dataData bit 7.
25CURSORvideoCursor from the 6845 (pin 19).
26DISENvideoDisplay enable from the 6845 (pin 18); low blanks the output.
27INVERTctrlReverse video select, link S26 (Model B).
28CRTC CLKclockCharacter clock to the 6845, 1 or 2 MHz by control register bit 4.

Fitted in

Sources