65SC12 CMOS CPU pinout
DIP-40. Main CPU of the Master. Runs every 6502 instruction plus the 65C02 additions.
A CMOS 6502 variant (Acorn calls it the 65C12) with the extra 65C02 instructions and addressing modes; BASIC IV assembles them. The Master drawing gives it three ground pins (1, 5, 21), DBE on pin 36 and SO tied high on 38; pins 3 and 35 are unused. A 6502A is not a drop-in: code that uses the new opcodes crashes. Test points TP3 (NMI), TP4 (IRQ), TP5 (SYNC), TP6 (R/W) sit beside it.
Open the interactive 65SC12 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | VSS | ground | Ground. |
| 2 | RDY | ctrl | Ready from the I/O controller (IC15 pin 17); also goes to the PBC. Low stretches the cycle. |
| 3 | NC | nc | Not connected on the Master (phi1 out on an NMOS 6502). UNVERIFIED |
| 4 | /IRQ | ctrl | Interrupt request (TP4). The memory controller, RTC (via LK4) and VIAs pull it. UNVERIFIED |
| 5 | VSS | ground | Ground (Master supply table lists 1, 5, 21). |
| 6 | /NMI | ctrl | Non-maskable interrupt (TP3): disk DRQ and Econet. |
| 7 | SYNC | ctrl | High on opcode fetch (TP5). The memory controller uses it for the shadow RAM rules. |
| 8 | VDD | power | +5 V. |
| 9 | A0 | addr | Address bit 0. |
| 10 | A1 | addr | Address bit 1. |
| 11 | A2 | addr | Address bit 2. |
| 12 | A3 | addr | Address bit 3. |
| 13 | A4 | addr | Address bit 4. |
| 14 | A5 | addr | Address bit 5. |
| 15 | A6 | addr | Address bit 6. |
| 16 | A7 | addr | Address bit 7. |
| 17 | A8 | addr | Address bit 8. |
| 18 | A9 | addr | Address bit 9. |
| 19 | A10 | addr | Address bit 10. |
| 20 | A11 | addr | Address bit 11. |
| 21 | VSS | ground | Ground. |
| 22 | A12 | addr | Address bit 12. |
| 23 | A13 | addr | Address bit 13. |
| 24 | A14 | addr | Address bit 14. |
| 25 | A15 | addr | Address bit 15. |
| 26 | D7 | data | Data bit 7 (CD7 bus). |
| 27 | D6 | data | Data bit 6. |
| 28 | D5 | data | Data bit 5. |
| 29 | D4 | data | Data bit 4. |
| 30 | D3 | data | Data bit 3. |
| 31 | D2 | data | Data bit 2. |
| 32 | D1 | data | Data bit 1. |
| 33 | D0 | data | Data bit 0. |
| 34 | R/W | ctrl | Read high, write low (TP6). |
| 35 | NC | nc | Not connected. |
| 36 | DBE | ctrl | Data bus enable, tied through R43/C19 on the Master. |
| 37 | PHI2 IN | clock | 2 MHz clock in, from the VIDPROC. Slow 1 MHz devices are handled by holding the cycle with RDY (pin 2, from the I/O controller IC15 pin 17), not by stretching this clock. |
| 38 | SO | ctrl | Set overflow, tied to +5VB. |
| 39 | PHI2 OUT | clock | phi2 out to the system. |
| 40 | /RES | ctrl | Reset, low on power-up and BREAK. |
Fitted in
- BBC Master 128 IC14