WD1770 / WD1772 floppy disk controller pinout

DIP-28. Single and double density floppy disk controller with built-in data separator and write precompensation.

A 179X-compatible controller with its own data separator and write precompensation, needing an 8 MHz clock on pin 18. The 1772 is the same chip with faster step rates. On the Master DRQ (pin 27) is inverted onto the CPU NMI by the I/O controller; INTRQ stuck high masks DRQ. Drive select and side come from a 74LS174 latch (IC4). Master probing (SM 7.8): /CS (pin 1) goes validly low when the filing system accesses the chip; the 8 MHz on pin 18 comes from IC19 pin 4 and VIDPROC pin 7; DRQ (pin 27) is low, going high once every 32 us while reading.

Open the interactive 1770 pinout

Pins

PinNameTypeSignal
1/CSctrlChip select.
2R/WctrlHigh = read, low = write.
3A0addrRegister select bit 0.
4A1addrRegister select bit 1 (status/command, track, sector, data).
5DAL0dataData bus bit 0.
6DAL1dataData bus bit 1.
7DAL2dataData bus bit 2.
8DAL3dataData bus bit 3.
9DAL4dataData bus bit 4.
10DAL5dataData bus bit 5.
11DAL6dataData bus bit 6.
12DAL7dataData bus bit 7.
13/MRctrlMaster reset (internal pull-up).
14GNDgroundGround.
15VCCpower+5 V +/-5%.
16STEPctrlStep pulse per head step.
17DIRCctrlDirection: high = stepping in.
18CLKclock8 MHz, 50% duty clock.
19/RDdataRaw read data from the drive.
20MOctrlMotor on.
21WGctrlWrite gate.
22WDdataWrite data (FM or MFM pulses).
23/TR00ctrlTrack 00 (internal pull-up).
24/IPctrlIndex pulse (internal pull-up).
25/WPRTctrlWrite protect (internal pull-up).
26/DDENctrlLow = double density (MFM).
27DRQctrlData request.
28INTRQctrlInterrupt request: set HIGH when a command completes; it stays HIGH until the Status Register is read or a new command is written.

Fitted in

Sources