Z80A CPU pinout

DIP-40. Main CPU (8-bit, 40-DIP)

Zilog Z80A: 8-bit NMOS CPU in 40 pins on +5 V alone. It runs warm. Check the clock at pin 6 and /RESET at pin 26 first: no clock, or /RESET stuck LOW, means no boot. Second sources (NEC 780C-1 and others) are pin for pin the same.

Open the interactive Z80A pinout

Pins

Pin	Name	Type	Signal
1	A11	addr	Address bit 11. Tri-states when the bus is released.
2	A12	addr	Address bit 12.
3	A13	addr	Address bit 13.
4	A14	addr	Address bit 14.
5	A15	addr	Address bit 15. Top bit of the 64K map.
6	CLK	clock	Single-phase MOS-level clock input. The machine's clock circuit sets the rate.
7	D4	data	Data bit 4.
8	D3	data	Data bit 3.
9	D5	data	Data bit 5.
10	D6	data	Data bit 6.
11	VCC	power	+5 V supply.
12	D2	data	Data bit 2.
13	D7	data	Data bit 7.
14	D0	data	Data bit 0.
15	D1	data	Data bit 1.
16	/INT	ctrl	Maskable interrupt request. Honored at the end of an instruction when interrupts are enabled.
17	/NMI	ctrl	Non-maskable interrupt, negative-edge triggered. Forces a restart at $0066 whatever the interrupt mask.
18	/HALT	ctrl	LOW after a HALT instruction until an NMI, an enabled maskable interrupt or a reset. The CPU keeps running NOPs for refresh.
19	/MREQ	ctrl	LOW when the address bus holds a valid memory address. Tri-state.
20	/IORQ	ctrl	LOW when A7-A0 hold a valid I/O port address; also LOW with /M1 in an interrupt acknowledge. Tri-state.
21	/RD	ctrl	LOW on a memory or I/O read. Tri-state.
22	/WR	ctrl	LOW when the data bus holds data to write. Tri-state.
23	/BUSAK	ctrl	Bus acknowledge (BUSACK in the Zilog manual): LOW when the CPU has released its buses.
24	/WAIT	ctrl	LOW adds wait states so slow memory or I/O can finish. Long waits stop DRAM refresh.
25	/BUSRQ	ctrl	Bus request (BUSREQ in the Zilog manual): LOW floats the CPU buses at the end of the machine cycle. A wired-OR bus request needs an external pull-up.
26	/RESET	ctrl	LOW for at least three clocks resets the CPU: PC, I and R cleared, interrupts off, mode 0.
27	/M1	ctrl	LOW during each opcode fetch; with /IORQ it marks an interrupt acknowledge.
28	/RFSH	ctrl	LOW with /MREQ in the refresh half of each opcode fetch; A6-A0 then hold a refresh address.
29	GND	ground	0 V.
30	A0	addr	Address bit 0.
31	A1	addr	Address bit 1.
32	A2	addr	Address bit 2.
33	A3	addr	Address bit 3.
34	A4	addr	Address bit 4.
35	A5	addr	Address bit 5.
36	A6	addr	Address bit 6.
37	A7	addr	Address bit 7.
38	A8	addr	Address bit 8.
39	A9	addr	Address bit 9.
40	A10	addr	Address bit 10.

Fitted in

ZX80 IC1
ZX81 IC3
ZX Spectrum 48K IC2
ZX Spectrum 128
ZX Spectrum +2 IC9
ZX Spectrum +3 IC2
Commodore 128 U10
ColecoVision U1
Coleco ADAM
Timex Sinclair 1000 IC3
Timex Sinclair 1500
Timex Sinclair 2068 U19
TRS-80 Model I Z40
TRS-80 Model III U77
TRS-80 Model 4 U57 (1983 board); U1 (gate-array board, Sams CSCS13)
Amstrad CPC 464 IC111 (Z8400APS)
Amstrad CPC 664 IC111 (Z8400APS)
Amstrad CPC 6128 IC111 (Z8400APS)
MSX1 (generic) Varies by maker; Z80A or a second source
MSX2 (generic) Varies by maker; Z80A or compatible, clocked from V9938 pin 8

Sources

Zilog Z80 CPU User Manual UM0080, Figure 3 Pin Configuration and Pin Functions, pp. 5-7