6567 / 6569 VIC-II pinout

DIP-40. Video + DRAM refresh + CPU clock

6567 NTSC, 6569 PAL. Vdd (pin 13) is +12 V; Vcc (pin 40) is +5 V. Makes the picture, refreshes the DRAM and sets the CPU clock and bus stealing. 8565/8562 are later 5 V HMOS-II parts. Runs hot.

Open the interactive VIC-II pinout

Pins

PinNameTypeSignal
1DB6dataVIC-II data bus bit 6 (DB0-DB11 are the 12-bit VIC bus to color and screen RAM).
2DB5dataVIC-II data bus bit 5.
3DB4dataVIC-II data bus bit 4.
4DB3dataVIC-II data bus bit 3.
5DB2dataVIC-II data bus bit 2.
6DB1dataVIC-II data bus bit 1.
7DB0dataVIC-II data bus bit 0.
8/IRQctrlInterrupt request to the CPU /IRQ. Open-drain, shared with CIA1.
9LPctrlLight pen input.
10/CSctrlChip select (address decoding). LOW to read or write VIC registers.
11R/WctrlRead/write from the CPU.
12BActrlBus Available. Goes LOW three cycles before the VIC-II takes the bus in the second clock phase (character fetches on a badline, sprite DMA); wired to CPU RDY.
13Vddpower+12 V supply on the 6567/6569 (sheet).
14COLORvideoChroma (color) output to the video DIN.
15S/LUMvideoLuminance and sync output to the video DIN.
16AECctrlAddress Enable Control. Drops LOW when the VIC takes the bus.
17Φ0clockClock output to the CPU Φ0 input and the timing chain.
18/RASctrlRow address strobe for the DRAM (refresh and video fetch).
19/CASctrlColumn address strobe for the DRAM.
20Vssground0 V.
21ΦCOLORclockColor clock input (PRG name PHCL): 14.31818 MHz NTSC from the clock circuit (PAL rate: see the machine clocks).
22ΦINclockDot clock input (PRG name PHIN): 8.18 MHz NTSC / 7.88 MHz PAL.
23A11addrVIC-II address bus bit 11 to the DRAM.
24A0addrAddress bit 0: multiplexed DRAM address out during VIC fetches; register-select input when the CPU reads or writes the VIC-II.
25A1addrAddress bit 1: DRAM address out during VIC fetches; register-select input during CPU access.
26A2addrAddress bit 2: DRAM address out during VIC fetches; register-select input during CPU access.
27A3addrAddress bit 3: DRAM address out during VIC fetches; register-select input during CPU access.
28A4addrAddress bit 4: DRAM address out during VIC fetches; register-select input during CPU access.
29A5addrAddress bit 5: DRAM address out during VIC fetches; register-select input during CPU access.
30A6addrVIC-II address bus bit 6 to the DRAM.
31A7addrVIC-II address bus bit 7 to the DRAM.
32A8addrVIC-II address bus bit 8 to the DRAM.
33A9addrVIC-II address bus bit 9 to the DRAM.
34A10addrVIC-II address bus bit 10 to the DRAM.
35DB11dataData bit 11, from the color RAM (DB8-DB11 are the color nybble). Input only (Bauer); DB0-DB7 are the bidirectional bus.
36DB10dataData bit 10, from the color RAM. Input only.
37DB9dataData bit 9, from the color RAM. Input only.
38DB8dataData bit 8, from the color RAM. Input only.
39DB7dataVIC-II data bus bit 7.
40Vccpower+5 V logic supply.

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