IIc TMG (Timing Generator) pinout

DIP-20. Master clock divider and RAM/video timing

Takes the 14.318 MHz master clock and makes 7M, the 3.58 MHz color reference, Φ0/Φ1, Q3, the RAM strobes /PRAS and /PCAS, and the video load and dot-clock signals. Dead TMG means no clocks: a completely dead IIc.

Open the interactive TMG pinout

Pins

PinNameTypeSignal
114Mclock14.318 MHz master timing input.
27Mclock7.159 MHz timing signal. UNVERIFIED
3CREFclock3.5795 MHz color reference.
4H0videoHorizontal video timing signal.
5VIDD7videoVideo data bit 7.
6SEGBvideoVideo timing signal.
7TEXTvideoVideo display text-modes enable. UNVERIFIED
8/CASENctrlRAM enable (CAS enable).
9/80COLvideoEnables 80-column display mode.
10GNDground0 V.
11/TMGENctrlEnables master timing. UNVERIFIED
12/LDPSvideoVideo shift-register load enable.
13VID7MclockVideo dot-clock enable: 7 MHz or steady 0.
14Φ1clockPhase 1 system clock.
15Φ0clockPhase 0 system clock.
16Q3clockIntermediate timing and strobe.
17/PCASctrlRAM column-address strobe.
18NCncReserved for testing.
19/PRASctrlRAM row-address strobe.
20+5Vpower+5 V.

Fitted in

Sources