Timex SCLD (TS2068) pinout

PLCC-68. Video, DRAM control, bank switching, clocks, keyboard, tape and beeper for the TS2068

The Timex custom chip, in a 68-pin J-lead chip carrier (PLCC), not a DIP: the drawing lays the 68 pins out as a strip, so go by number. It divides the 14.112 MHz crystal to the 3.528 MHz CPU clock and the 1.764 MHz AY clock, makes U, V and Y video and TTL RGB, drives the 4416 RAS/CAS/MUX, selects the Home ROM, Extension ROM and dock, scans the keyboard and runs tape and beeper. Pins from the Timex schematic (U3); a traced CATS pinout agrees on all but four pins.

Open the interactive SCLD pinout

Pins

PinNameTypeSignal
1A0addrAddress bit 0 from the Z80A.
2A1addrAddress bit 1.
3A2addrAddress bit 2.
4A3addrAddress bit 3.
5A4addrAddress bit 4.
6A5addrAddress bit 5.
7A6addrAddress bit 6.
8A7addrAddress bit 7.
9A13addrAddress bit 13 (bank chunk decode).
10/ΦclockBuffered, inverted CPU clock out to the system bus (P1 B9).
11/EXROMctrlExtension ROM select: to U20 pin 20, P1 A27 and dock pin 34.
12/BEctrlBank enable from P1 A29 / dock pin 33. LOW disables the internal Home, Extension and Dock banks for external memory.
13OSC OUTclockCrystal oscillator amplifier output, drives the 14.112 MHz crystal. UNVERIFIED
14OSC INclockCrystal oscillator amplifier input. UNVERIFIED
15TAPE INaudioCassette signal input from the EAR circuit.
16SPKR/TAPE OUTaudioDigital output to the MIC circuit and the beeper amplifier (also P1 B2).
17BC1ctrlBus control 1 to AY-3-8912 pin 20.
18BDIRctrlBus direction to AY-3-8912 pin 18.
19ΦCclockSound chip clock to AY-3-8912 pin 15.
20/TSctrlTri-state control for the address and data buffers when the CPU and the video logic both want display RAM.
21MUXctrlRow/column select to the 74LS157 address multiplexers U10 and U11.
22MA7addrDisplay memory multiplexed address bit 7.
23MA3addrDisplay memory multiplexed address bit 3.
24MA4addrDisplay memory multiplexed address bit 4.
25MA2addrDisplay memory multiplexed address bit 2.
26GNDgroundGround.
27/ROMCSctrlHome ROM chip select (U16 pin 20) when the Home Bank is selected.
28MA6addrDisplay memory multiplexed address bit 6. UNVERIFIED
29MA1addrDisplay memory multiplexed address bit 1.
30MA5addrDisplay memory multiplexed address bit 5. UNVERIFIED
31MA0addrDisplay memory multiplexed address bit 0.
32/ROSCSctrlROM-oriented software (dock bank) chip select to dock pin 35 and P1 A28.
33YvideoLuminance level to the LM1889 modulator U4.
34UvideoChroma vector U (B-Y) to the LM1889.
35VvideoChroma vector V (R-Y) to the LM1889.
36/RAS1ctrlRow address strobe for the display RAM (U6, U7).
37/DRAMWEctrlWrite enable for the display RAM only.
38A7RaddrAddress bit 7 plus refresh, to the upper 32K of 4416s (via U5).
39/CAS3ctrlColumn address strobe, Home Bank RAM 4th 16K ($C000-$FFFF).
40/CAS2ctrlColumn address strobe, Home Bank RAM 3rd 16K ($8000-$BFFF).
41/CAS1ctrlColumn address strobe, display RAM (2nd 16K, $4000-$7FFF).
42ΦCPUclockCPU clock to Z80A pin 6. Held HIGH while the video logic owns display RAM.
43VCCpower+5 V supply.
44A14addrAddress bit 14.
45A15addrAddress bit 15.
46BvideoBlue TTL color out to P1 B29.
47GvideoGreen TTL color out to P1 B28.
48RvideoRed TTL color out to P1 B27.
49KB0kbdKeyboard line 0 (J9 pin 1).
50KB1kbdKeyboard line 1 (J9 pin 2).
51KB2kbdKeyboard line 2 (J9 pin 3).
52KB3kbdKeyboard line 3 (J9 pin 4).
53KB4kbdKeyboard line 4 (J9 pin 5).
54RDIRctrlRead direction control for the 74LS245 data buffer U9 between CPU and SCLD (drawn RD with an overbar on the schematic, RD* in CATS).
55D1dataData bit 1 (SCLD side of U9, shared with display RAM).
56D2dataData bit 2.
57D0dataData bit 0.
58D3dataData bit 3.
59D5dataData bit 5.
60D6dataData bit 6.
61D4dataData bit 4.
62D7dataData bit 7.
63/RDctrlRead strobe from the Z80A.
64/IORQctrlI/O request from the Z80A.
65/WRctrlWrite strobe from the Z80A.
66/MREQctrlMemory request from the Z80A.
67/INTctrlInterrupt to the Z80A for keyboard scan and PAUSE timing. Open drain with internal pull-up.
68/RFSHctrlRefresh from the Z80A.

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