MMU 344-0010 pinout

DIP-40. Memory Management Unit

Memory Management Unit of the IIe: main/auxiliary bank switching, language-card RAM over the ROMs, /INH and /DMA handling, and the multiplexed RAM address RA0-RA7 for CPU cycles. With the IOU it replaces the discrete TTL of the II/II+. Shares RA0-RA7 and MD7 with the IOU. Pinout from the IIe Technical Reference Manual. Part number 344-0010 (marked 344-0010-B) from the Sams CC10 parts list, which reads the fitted chips; Apple schematic 050-0051-D prints 344-0100 in the UE4 box. No other source gives 344-0100, so treat it as a drafting slip and order 344-0010.

Open the interactive MMU pinout

Pins

Pin	Name	Type	Signal
1	GND	ground	0 V.
2	A0	addr	65C02 address bit 0.
3	PHI0	clock	System clock 1.023 MHz.
4	Q3	clock	2 MHz asymmetric timing clock.
5	/PRAS	ctrl	Pre-RAS timing for DRAM.
6	RA0	addr	Multiplexed RAM address 0 (row, then column), shared with the IOU.
7	RA1	addr	Multiplexed RAM address 1 (row, then column), shared with the IOU.
8	RA2	addr	Multiplexed RAM address 2 (row, then column), shared with the IOU.
9	RA3	addr	Multiplexed RAM address 3 (row, then column), shared with the IOU.
10	RA4	addr	Multiplexed RAM address 4 (row, then column), shared with the IOU.
11	RA5	addr	Multiplexed RAM address 5 (row, then column), shared with the IOU.
12	RA6	addr	Multiplexed RAM address 6 (row, then column), shared with the IOU.
13	RA7	addr	Multiplexed RAM address 7 (row, then column), shared with the IOU.
14	R/W	ctrl	Read/Write from CPU.
15	/INH	ctrl	Inhibit: a card pulls LOW to switch off motherboard ROM/RAM. Pulled up to +5 V.
16	/DMA	ctrl	A card takes the bus.
17	/EN80	ctrl	Enable auxiliary (80-column) RAM.
18	/KBD	ctrl	Keyboard register select ($C000).
19	/ROMEN2	ctrl	ROM enable for $E000-$FFFF. A separate net from /ROMEN1 on the board (TRM Table 7-6 says they are tied; the schematic and Sather do not): do not bridge them.
20	/ROMEN1	ctrl	ROM enable for $C100-$CFFF and $D000-$DFFF. A separate net from /ROMEN2 (see pin 19).
21	MD7	data	Data bit 7: the MMU reports its soft-switch state here through a three-state output (shared with the IOU).
22	R/W245	ctrl	Direction control for the 74LS245 data-bus buffer.
23	/RAMEN	ctrl	Enables main RAM.
24	Cxxx	ctrl	Enables the $C000-$CFFF I/O and peripheral decoding (built-in I/O at $C0xx and card space), subject to the ROM-select soft switches that take over parts of $C100-$CFFF.
25	Vcc	power	+5 V.
26	A15	addr	Address bus bit 15.
27	A14	addr	Address bus bit 14.
28	A13	addr	Address bus bit 13.
29	A12	addr	Address bus bit 12.
30	A11	addr	Address bus bit 11.
31	A10	addr	Address bus bit 10.
32	A9	addr	Address bus bit 9.
33	A8	addr	Address bus bit 8.
34	A7	addr	Address bus bit 7.
35	A6	addr	Address bus bit 6.
36	A5	addr	Address bus bit 5.
37	A4	addr	Address bus bit 4.
38	A3	addr	Address bus bit 3.
39	A2	addr	Address bus bit 2.
40	A1	addr	Address bus bit 1.

Fitted in

Apple IIe UE4 (Apple schematic 050-0051-D; Sams CC10 agrees)

MMU 344-0010 pinout

Pins

Fitted in

Sources