IIc MMU (Memory Management Unit) pinout
DIP-40. Memory management and RAM address multiplex
The IIc version of the IIe MMU: main/auxiliary banking, language-card RAM, the ROM enables and the RAM address multiplex for CPU cycles. It also decodes $C06x and $C07x for the hand-control and mouse circuits and the SELIO select for the GLU and IOU. Reports its soft switches on MD7.
Open the interactive MMU pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | GND | ground | 0 V. |
| 2 | A0 | addr | 65C02 address bit 0. |
| 3 | Φ0 | clock | Clock phase 0 input. |
| 4 | Q3 | clock | Timing signal input (2 MHz, asymmetric). |
| 5 | /PRAS | ctrl | Memory row-address strobe. |
| 6 | RA0 | addr | Multiplexed RAM address 0. |
| 7 | RA1 | addr | Multiplexed RAM address 1. |
| 8 | RA2 | addr | Multiplexed RAM address 2. |
| 9 | RA3 | addr | Multiplexed RAM address 3. |
| 10 | RA4 | addr | Multiplexed RAM address 4. |
| 11 | RA5 | addr | Multiplexed RAM address 5. |
| 12 | RA6 | addr | Multiplexed RAM address 6. |
| 13 | RA7 | addr | Multiplexed RAM address 7. |
| 14 | R/W | ctrl | 65C02 read/write. |
| 15 | /INH | ctrl | Inhibits main memory; tied to +5 V on the IIc. |
| 16 | /C06X | ctrl | Goes LOW during Φ0 for $C06x (hand-control and switch reads). |
| 17 | /EN80 | ctrl | Enables auxiliary RAM. |
| 18 | /KBD | ctrl | Enables keyboard data bits 0-6 onto the bus. |
| 19 | /ROMEN2 | ctrl | ROM enable; tied to /ROMEN1. |
| 20 | /ROMEN1 | ctrl | ROM enable; tied to /ROMEN2. |
| 21 | MD7 | data | MMU soft-switch status on data bit 7. |
| 22 | /C07X | ctrl | Goes LOW during Φ0 for $C07x (paddle timer reset). |
| 23 | /CASEN | ctrl | Enables main RAM. |
| 24 | /SELIO | ctrl | LOW during Φ0 for any $C0xx access except $C08x, $C0Bx, $C0Cx and $C0Fx. |
| 25 | +5V | power | +5 V. |
| 26 | A15 | addr | 65C02 address bit 15. |
| 27 | A14 | addr | 65C02 address bit 14. |
| 28 | A13 | addr | 65C02 address bit 13. |
| 29 | A12 | addr | 65C02 address bit 12. |
| 30 | A11 | addr | 65C02 address bit 11. |
| 31 | A10 | addr | 65C02 address bit 10. |
| 32 | A9 | addr | 65C02 address bit 9. |
| 33 | A8 | addr | 65C02 address bit 8. |
| 34 | A7 | addr | 65C02 address bit 7. |
| 35 | A6 | addr | 65C02 address bit 6. |
| 36 | A5 | addr | 65C02 address bit 5. |
| 37 | A4 | addr | 65C02 address bit 4. |
| 38 | A3 | addr | 65C02 address bit 3. |
| 39 | A2 | addr | 65C02 address bit 2. |
| 40 | A1 | addr | 65C02 address bit 1. |