74LS323 8-bit universal shift/storage register pinout
DIP-20. Controller data register (shifts disk bits in and out)
The data register between the 6502 and the drive. P6 sets its mode on S0/S1 and /CLR every Q3 cycle: load from the bus to write, shift left to assemble read bits, shift right to sample the write-protect line at SR. Its 3-state I/O pins drive the data bus only on even $C08x,X reads (/G2 is address bit 0) with /DEVICE SELECT LOW.
Open the interactive 74LS323 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | S0 | ctrl | Function select 0, from the P6 sequencer command. |
| 2 | /G1 | ctrl | Output control 1: /DEVICE SELECT (slot pin 41). |
| 3 | /G2 | ctrl | Output control 2: address bit A0, so only even addresses read the register. |
| 4 | G/QG | data | Register bit G, to the slot data bus. |
| 5 | E/QE | data | Register bit E, to the slot data bus. |
| 6 | C/QC | data | Register bit C, to the slot data bus. |
| 7 | A/QA | data | Register bit A, to the slot data bus. |
| 8 | QA' | data | Serial output of stage A: to P6 address A1. |
| 9 | /CLR | ctrl | Synchronous clear, from the sequencer. |
| 10 | GND | ground | 0 V. |
| 11 | SR | io | Shift-right serial input: W PROT from ribbon pin 20. |
| 12 | CLK | clock | Clock: Q3 gated through the 74LS132 while a drive is on. |
| 13 | B/QB | data | Register bit B, to the slot data bus. |
| 14 | D/QD | data | Register bit D, to the slot data bus. |
| 15 | F/QF | data | Register bit F, to the slot data bus. |
| 16 | H/QH | data | Register bit H, to the slot data bus. |
| 17 | QH' | data | Serial output of stage H (not used on the Disk II card). |
| 18 | SL | io | Shift-left serial input, from the sequencer. |
| 19 | S1 | ctrl | Function select 1, from the P6 sequencer command. |
| 20 | VCC | power | +5 V. |
Fitted in
- Disk II C3 on the Disk II Interface Card
- DuoDisk 74LS323 on the 5.25 controller card
- UniDisk 5.25 74LS323 on the 5.25 controller card (II/IIe hosts only)