74LS174 hex D flip-flop pinout
DIP-16. Sequencer state latch and read-pulse synchronizer
Four flip-flops hold the sequencer state (P6 outputs D4-D7 in, fed back to P6 address lines A0, A5, A6, A7); two more clock RD DATA through twice to line it up with Q3. Clocked on Q3, cleared when the drives go off, and powered with P6 through Q3 (MPSU51) only while a drive is on, so 0 V on pin 16 with the drives off is normal.
Open the interactive 74LS174 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | /CLR | ctrl | Clear, from the drive-on logic: drives off clears the sequencer. |
| 2 | 1Q | data | Schematic Q0: state bit to P6 A7 (also the write-data toggle). |
| 3 | 1D | data | Schematic D0: from P6 D7 (pin 14). |
| 4 | 2D | data | Schematic D1: from P6 D6 (pin 13). |
| 5 | 2Q | data | Schematic Q1: state bit to P6 A6. |
| 6 | 3D | data | Schematic D2: from P6 D4 (pin 11). |
| 7 | 3Q | data | Schematic Q2: state bit to P6 A5. |
| 8 | GND | ground | 0 V. |
| 9 | CLK | clock | Clock: Q3 through the 74LS132. |
| 10 | 4Q | io | Schematic Q3: twice-latched read pulse to the 74LS132 and P6 A4. |
| 11 | 4D | io | Schematic D3: from 5Q (pin 12), the second synchronizer stage. |
| 12 | 5Q | io | Schematic Q4: first latched copy of the read pulse. |
| 13 | 5D | io | Schematic D4: RD DATA from ribbon pin 16. |
| 14 | 6D | data | Schematic D5: from P6 D5 (pin 12). |
| 15 | 6Q | data | Schematic Q5: state bit to P6 A0. |
| 16 | VCC | power | +5 V, switched by Q3 (MPSU51) only while a drive is on. |
Fitted in
- Disk II A3 on the Disk II Interface Card
- DuoDisk 74LS174 on the 5.25 controller card
- UniDisk 5.25 74LS174 on the 5.25 controller card (II/IIe hosts only)