IOU 344-0020 pinout
DIP-40. Input/Output Unit
Input/Output Unit of the IIe: video counters and timing (SYNC, WNDW, CLRGAT, H0, VC, SEGA, SEGB), the display soft switches, speaker, cassette out, annunciators, keyboard strobe and any-key-down, and the power-on /RESET. Pinout from the IIe Technical Reference Manual (pin 28 is +5 V). Apple schematic 050-0051-D sheet 3 labels it UE5, 344-0020; Sams CC10 lists 344-0020-A.
Open the interactive IOU pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | GND | ground | 0 V. |
| 2 | GR | video | Graphics mode enable. |
| 3 | SEGA | video | Text: with SEGB and VC selects the dot row of the character. |
| 4 | SEGB | video | Text: with SEGA and VC selects the dot row. Graphics: LOW selects hi-res, HIGH lo-res. |
| 5 | VC | video | Vertical counter bit. Text: third row-select bit. Lo-res: picks the upper or lower block of a byte. |
| 6 | /80VID | video | 80-column video enable. |
| 7 | CASSO | audio | Cassette output toggle. |
| 8 | SPKR | audio | Speaker toggle ($C030). |
| 9 | MD7 | data | Data bit 7: the IOU reports its soft-switch flags here through a three-state output (shared with the MMU). |
| 10 | AN0 | io | Annunciator 0 (game I/O). |
| 11 | AN1 | io | Annunciator 1. |
| 12 | AN2 | io | Annunciator 2. |
| 13 | AN3 | io | Annunciator 3. |
| 14 | R/W | ctrl | Read/Write from CPU. |
| 15 | /RESET | ctrl | Power-on reset: the IOU holds it LOW at power-up and also responds to RESET (Sather p. 4-2). |
| 16 | NC | nc | No connection. |
| 17 | RA0 | addr | Multiplexed RAM address 0. The IOU drives video and refresh addresses in phase 1. |
| 18 | RA1 | addr | Multiplexed RAM address 1. The IOU drives video and refresh addresses in phase 1. |
| 19 | RA2 | addr | Multiplexed RAM address 2. The IOU drives video and refresh addresses in phase 1. |
| 20 | RA3 | addr | Multiplexed RAM address 3. The IOU drives video and refresh addresses in phase 1. |
| 21 | RA4 | addr | Multiplexed RAM address 4. The IOU drives video and refresh addresses in phase 1. |
| 22 | RA5 | addr | Multiplexed RAM address 5. The IOU drives video and refresh addresses in phase 1. |
| 23 | RA6 | addr | Multiplexed RAM address 6. The IOU drives video and refresh addresses in phase 1. |
| 24 | RA7 | addr | Multiplexed RAM address 7. The IOU drives video and refresh addresses in phase 1. |
| 25 | /PRAS | ctrl | Row-address strobe (phase 0). |
| 26 | PHI0 | clock | Clock phase 0 (1.023 MHz). |
| 27 | Q3 | clock | Intermediate timing signal (2 MHz, asymmetric). |
| 28 | Vcc | power | +5 V. |
| 29 | A6 | addr | Address bit 6 (soft-switch decode). |
| 30 | /C0XX | ctrl | I/O address enable: address is in $C000-$C0FF. |
| 31 | AKD | kbd | Any-key-down from the keyboard encoder. |
| 32 | KSTRB | kbd | Keyboard strobe from the keyboard encoder. |
| 33 | VID7 | video | Video display data bit 7. |
| 34 | VID6 | video | Video display data bit 6. |
| 35 | /RA9 | addr | Video display control bit (to the character generator). |
| 36 | /RA10 | addr | Video display control bit (to the character generator). |
| 37 | /CLRGAT | video | Color-burst gate (enable). |
| 38 | /WNDW | video | Display window: HIGH during horizontal or vertical blanking (it then disables the video ROM), LOW during active video. |
| 39 | /SYNC | video | Display synchronization (composite sync). |
| 40 | H0 | video | Horizontal timing: low bit of the character counter. |
Fitted in
- Apple IIe UE5 (Apple schematic 050-0051-D sheet 3; Sams CC10 agrees)