IIc IOU (Input/Output Unit) pinout
DIP-40. Video timing, soft switches, mouse and keyboard I/O
The IIc version of the IIe IOU: video counters and sync, the display soft switches, speaker, keyboard strobe and any-key-down, plus mouse movement inputs and the VBL/mouse interrupt (/IRQ on pin 16). The cassette output pin is reserved on the IIc.
Open the interactive IOU pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | GND | ground | 0 V. |
| 2 | GR | video | Graphics mode enable. |
| 3 | SEGA | video | Text: with SEGB and VC selects the dot row of the character. |
| 4 | SEGB | video | Text: row select with SEGA and VC. Graphics: LOW hi-res, HIGH lo-res. |
| 5 | VC | video | Vertical counter bit (row select; lo-res upper/lower block). |
| 6 | /80COL | video | 80-column video enable. |
| 7 | CASSO | io | Reserved on the IIc. |
| 8 | SPKR | audio | Speaker output signal. |
| 9 | MD7 | data | IOU flags onto data bit 7. |
| 10 | YMOVE | io | Mouse movement along Y. |
| 11 | NC | nc | Not used. |
| 12 | NC | nc | Not used. |
| 13 | PDL0/XMOVE | io | Mouse movement along X (shared with paddle 0). |
| 14 | R/W | ctrl | 65C02 read/write. |
| 15 | /RESET | ctrl | Power-on and reset output. |
| 16 | /IRQ | ctrl | Maskable interrupt to the 65C02 (mouse, VBL). |
| 17 | RA0 | addr | Multiplexed RAM address 0; video refresh address in phase 1. UNVERIFIED |
| 18 | RA1 | addr | Multiplexed RAM address 1; video refresh address in phase 1. UNVERIFIED |
| 19 | RA2 | addr | Multiplexed RAM address 2; video refresh address in phase 1. UNVERIFIED |
| 20 | RA3 | addr | Multiplexed RAM address 3; video refresh address in phase 1. UNVERIFIED |
| 21 | RA4 | addr | Multiplexed RAM address 4; video refresh address in phase 1. UNVERIFIED |
| 22 | RA5 | addr | Multiplexed RAM address 5; video refresh address in phase 1. UNVERIFIED |
| 23 | RA6 | addr | Multiplexed RAM address 6; video refresh address in phase 1. UNVERIFIED |
| 24 | RA7 | addr | Multiplexed RAM address 7; video refresh address in phase 1. UNVERIFIED |
| 25 | /PRAS | ctrl | Row-address strobe (phase 0). |
| 26 | Φ0 | clock | Clock phase 0. |
| 27 | Q3 | clock | Intermediate timing signal (2 MHz). |
| 28 | +5V | power | +5 V. |
| 29 | A6 | addr | 65C02 address bit 6. |
| 30 | /IOUSELIO | ctrl | IOU select, derived from the MMU /SELIO by the GLU. |
| 31 | AKD | kbd | Any-key-down. |
| 32 | KSTRB | kbd | Keyboard strobe. |
| 33 | VIDD7 | video | Video display data bit 7. |
| 34 | VIDD6 | video | Video display data bit 6. |
| 35 | /RA9 | video | Video display control bit. |
| 36 | /RA10 | video | Video display control bit. |
| 37 | /CLRGAT | video | Color-burst gate (enable). |
| 38 | /WNDW | video | Display blanking. |
| 39 | /SYNC | video | Display synchronization. |
| 40 | H0 | video | Horizontal timing: low bit of the character counter. |