IIe timing HAL 342-0170 (HAL/PAL 16R8) pinout

DIP-20. Divides the 14M master clock into PHI0, PHI1, Q3, the RAM strobes and the video load and dot-clock signals UNVERIFIED

A mask-programmed 16R8 (Apple 342-0170) clocked by 14M on pin 1. Its registered outputs make PHI0, PHI1 and Q3, the RAM strobes /PRAS and /PCAS, and the video signals /LDPS and VID7M. A dead HAL stops every clock after the oscillator, so the IIe is completely dead. Sams: clock at UE1 but none at the CPU means UC1, this HAL, UE1 or UB8. Pin names are as drawn on the Apple schematic; some input nets are not legible there.

Open the interactive HAL pinout

Pins

PinNameTypeSignal
1CPclockRegister clock: 14M, the 14.318 MHz master clock.
2I0ctrlInput 0. Its net is not legible on the schematic. UNVERIFIED
3I1ctrlInput 1, from the Q output (pin 10) of the S109 flip-flop at UC1.
4I5videoInput 5: H0, horizontal timing from the IOU.
5I3videoInput 3: VID7, video data bit 7.
6I4videoInput 4: SEGB, video segment timing.
7I2ctrlInput 2. Its net is not legible on the schematic. UNVERIFIED
8I6ctrlInput 6. Its net is not legible on the schematic. UNVERIFIED
9I7videoInput 7: /80VID, 80-column video mode.
10GNDgroundGround (the usual 16R8 pin; not drawn on the schematic). UNVERIFIED
11/OEctrlOutput enable for the registered outputs.
12/LDPSvideoOutput 7: load pulse for the video shift register.
13VID7MvideoOutput 6: video dot-clock enable.
14PHI1clockOutput 5: PHI1 system clock (Sams probes it here).
15PHI0clockOutput 4: PHI0 system clock.
16Q3clockOutput 3: Q3 timing strobe (Sams probes it here).
17/PCASctrlOutput 2: RAM column strobe, read by elimination from the outputs drawn at the sheet edge. UNVERIFIED
18O1ncOutput 1; no net is drawn on it. UNVERIFIED
19/PRASctrlOutput 0: RAM row strobe (Sams probes it here).
20VCCpower+5 V (the usual 16R8 pin; not drawn on the schematic). UNVERIFIED

Fitted in

Sources