IIc GLU (General Logic Unit) pinout
DIP-24. I/O decode, RAM read/write timing, double hi-res
Miscellaneous logic in one chip: RAM read/write timing, double hi-res enable and soft switches, soft-switch status and write registers, mouse-interrupt control for the IOU, and the device selects for the IWM (/DISK) and the 6551s (/SER). A bad GLU can kill disk and serial access together.
Open the interactive GLU pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | 14M | clock | Master clock (14.318 MHz). |
| 2 | A0 | addr | Address bit 0 (low byte of $C0xx). |
| 3 | A3 | addr | Address bit 3 (low byte of $C0xx). |
| 4 | A4 | addr | Address bit 4 (low byte of $C0xx). |
| 5 | A5 | addr | Address bit 5 (low byte of $C0xx). |
| 6 | A6 | addr | Address bit 6 (low byte of $C0xx). |
| 7 | A7 | addr | Address bit 7 (low byte of $C0xx). |
| 8 | Φ0 | clock | Phase 0 of the 1.0227 MHz processor clock. |
| 9 | /SELIO | ctrl | I/O page select from the MMU. |
| 10 | GR | video | Graphics mode select line. |
| 11 | /RESET | ctrl | Master reset; resets the GLU. |
| 12 | GND | ground | 0 V. |
| 13 | /GLUEN | ctrl | Enables the GLU. UNVERIFIED |
| 14 | MD7 | data | Status of MMU flags on data bit 7. UNVERIFIED |
| 15 | R/W | ctrl | Read/write qualifier from the processor. |
| 16 | TEXT | video | Video timing signal for double hi-res or non-graphics modes. UNVERIFIED |
| 17 | NC | nc | Not used. |
| 18 | NC | nc | Not used. |
| 19 | CREF | clock | Color reference signal, 3.58 MHz from the TMG. |
| 20 | 7M | clock | 7 MHz clock output. |
| 21 | /DISK | ctrl | Disk controller (IWM) device select. |
| 22 | IOUHOLE | ctrl | Controls /IOUSELIO to the IOU. |
| 23 | /SER | ctrl | Serial controller (6551) device select. |
| 24 | +5V | power | +5 V. |