WD FD1793 floppy disk formatter/controller pinout

DIP-40. Single and double density disk controller on the Model III and Model 4 FDC boards, ports F0H-F3H.

FM and MFM controller with a true (non-inverted) data bus; the 1791 is the same chip with an inverted bus. It needs +5 V (pin 21) and +12 V (pin 40). On the Model III and 4 FDC boards it is clocked at 1 MHz, uses a WD1691 for write precompensation and data separation and a WD2143 clock generator, and drives the CPU through the NMI logic. Its registers are ports F0H (command/status), F1H (track), F2H (sector) and F3H (data).

Open the interactive 1793 pinout

Pins

Pin	Name	Type	Signal
1	NC	nc	Internally tied to a back-bias generator. Must be left open.
2	/WE	ctrl	Write enable. LOW gates the DAL into the selected register while /CS is LOW.
3	/CS	ctrl	Chip select. LOW enables communication with the CPU.
4	/RE	ctrl	Read enable. LOW puts the selected register on the DAL while /CS is LOW.
5	A0	addr	Register select bit 0. A1 A0: 00 status/command, 01 track, 10 sector, 11 data.
6	A1	addr	Register select bit 1.
7	DAL0	data	Data access line 0. True (non-inverted) on the 1793.
8	DAL1	data	Data access line 1. True (non-inverted) on the 1793.
9	DAL2	data	Data access line 2. True (non-inverted) on the 1793.
10	DAL3	data	Data access line 3. True (non-inverted) on the 1793.
11	DAL4	data	Data access line 4. True (non-inverted) on the 1793.
12	DAL5	data	Data access line 5. True (non-inverted) on the 1793.
13	DAL6	data	Data access line 6. True (non-inverted) on the 1793.
14	DAL7	data	Data access line 7. True (non-inverted) on the 1793.
15	STEP	ctrl	Step output: one pulse per step.
16	DIRC	ctrl	Direction: HIGH steps in, LOW steps out.
17	EARLY	ctrl	HIGH: shift the current write pulse early (precompensation).
18	LATE	ctrl	HIGH: shift the current write pulse late (precompensation).
19	/MR	ctrl	Master reset. LOW loads 03H into the command register; a restore runs when it goes HIGH and the sector register becomes 01H.
20	VSS	ground	Ground.
21	VCC	power	+5 V ±5 %.
22	/TEST	ctrl	Test input. Tie to +5 V or leave open except with voice-coil drives.
23	HLT	ctrl	Head load timing. HIGH means the head is engaged.
24	CLK	clock	Free-running clock: 2 MHz for 8-inch drives, 1 MHz for mini drives.
25	RG	ctrl	Read gate (1791/1793): HIGH when a field of zeros or ones is found, for data separator sync. (SSO side select on the 1795/1797.)
26	RCLK	clock	Read clock from the data separator (WD1691 on the Model III board). Phase matters, polarity does not.
27	/RAW READ	data	Raw read data from the drive: one negative pulse per flux transition.
28	HLD	ctrl	Head load. Controls loading of the head against the disk.
29	TG43	ctrl	Track greater than 43. Valid only during read and write commands.
30	WG	ctrl	Write gate. Goes valid before writing.
31	WD	data	Write data: a 250 ns (MFM) or 500 ns (FM) pulse per flux transition.
32	READY	ctrl	Drive ready. Must be HIGH for reads and writes; appears inverted as status bit 7. Type I commands ignore it.
33	/WF/VFOE	ctrl	Write fault input while WG = 1 (LOW ends the write); VFO enable output while WG = 0, LOW during reads once the head has settled.
34	/TR00	ctrl	Track 00. LOW when the head is over track 0.
35	/IP	ctrl	Index pulse from the drive.
36	/WPRT	ctrl	Write protect. Sampled on a write command; LOW ends it and sets the write-protect status bit.
37	/DDEN	ctrl	Double density select. LOW = MFM, HIGH = FM. Model III: from port F4H bit 7 (bit set selects MFM).
38	DRQ	ctrl	Data request, open drain (10 kΩ pull-up): the data register is full on a read or empty on a write. Model III: DRQ clears the CPU wait state; the end-of-transfer NMI comes from INTRQ, not DRQ.
39	INTRQ	ctrl	Interrupt request, open drain. Set at the end of any command; reset by reading status or writing a command.
40	VDD	power	+12 V ±5 %.

Fitted in

TRS-80 Model III U7 on the FDC board (Sams)
TRS-80 Model 4 U6 on FDC board 8858160

WD FD1793 floppy disk formatter/controller pinout

Pins

Fitted in

Sources