6510 CPU pinout
DIP-40. CPU
C64 CPU at ~1 MHz with a 6-bit I/O port (P0-P5) for bank switching and the Datasette. Same core as the 6502; the port is the difference.
Open the interactive 6510 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | Φ1 IN | clock | Clock input (data sheet name Φ1 IN). On the C64 it is fed from the VIC-II Φ0 output (VIC pin 17). |
| 2 | RDY | ctrl | Ready. The VIC-II pulls this LOW through BA to stall the CPU on badlines. |
| 3 | /IRQ | ctrl | Interrupt request from CIA1 and the VIC-II. |
| 4 | /NMI | ctrl | Non-maskable interrupt, from CIA2 (sheet). |
| 5 | AEC | ctrl | Address Enable Control. VIC-II takes it LOW to tri-state the CPU address bus during its own fetches. |
| 6 | Vcc | power | +5 V logic supply. |
| 7 | A0 | addr | Address bus bit 0. |
| 8 | A1 | addr | Address bus bit 1. |
| 9 | A2 | addr | Address bus bit 2. |
| 10 | A3 | addr | Address bus bit 3. |
| 11 | A4 | addr | Address bus bit 4. |
| 12 | A5 | addr | Address bus bit 5. |
| 13 | A6 | addr | Address bus bit 6. |
| 14 | A7 | addr | Address bus bit 7. |
| 15 | A8 | addr | Address bus bit 8. |
| 16 | A9 | addr | Address bus bit 9. |
| 17 | A10 | addr | Address bus bit 10. |
| 18 | A11 | addr | Address bus bit 11. |
| 19 | A12 | addr | Address bus bit 12. |
| 20 | A13 | addr | Address bus bit 13. |
| 21 | GND | ground | 0 V. |
| 22 | A14 | addr | Address bus bit 14. |
| 23 | A15 | addr | Address bus bit 15. |
| 24 | P5 | io | Port bit 5: Datasette motor control output (LOW = motor on). |
| 25 | P4 | io | Port bit 4: Datasette sense input (play key down). |
| 26 | P3 | io | Port bit 3: Datasette write output (cassette port pins E/5). |
| 27 | P2 | io | Processor port bit 2: /CHAREN, character ROM or I/O at $D000. |
| 28 | P1 | io | Processor port bit 1: /HIRAM, KERNAL ROM at $E000. |
| 29 | P0 | io | Processor port bit 0: /LORAM, BASIC ROM at $A000. |
| 30 | D7 | data | Data bus bit 7. |
| 31 | D6 | data | Data bus bit 6. |
| 32 | D5 | data | Data bus bit 5. |
| 33 | D4 | data | Data bus bit 4. |
| 34 | D3 | data | Data bus bit 3. |
| 35 | D2 | data | Data bus bit 2. |
| 36 | D1 | data | Data bus bit 1. |
| 37 | D0 | data | Data bus bit 0. |
| 38 | R/W | ctrl | Read/write from the CPU. HIGH = read, LOW = write. |
| 39 | Φ2 OUT | clock | Phase 2 system clock out. Feeds the CIA (pin 25) and SID (pin 6) Φ2 inputs. UNVERIFIED |
| 40 | /RES | ctrl | Reset. LOW at power-up, released HIGH so the CPU reads its reset vector. |
Fitted in
- Commodore 64 U7
Sources
- CSG 6510 Microprocessor with I/O data sheet, p. 1 pin configurations (GIF scans)
- C64 Programmer's Reference Guide, App. L, p. 403 pin configuration
- C64/C64C Service Manual, cassette interface (P3-P5), p. 11
- Ray Carlsen, C64C chips vs common symptoms (c64c-ic.txt), Wayback Machine copy (2025)
- Ray Carlsen, VIC and CPU substitutions in the C64C board 250469, Wayback Machine copy (2026)