6510 CPU pinout

DIP-40. CPU

C64 CPU at ~1 MHz with a 6-bit I/O port (P0-P5) for bank switching and the Datasette. Same core as the 6502; the port is the difference.

Open the interactive 6510 pinout

Pins

PinNameTypeSignal
1Φ1 INclockClock input (data sheet name Φ1 IN). On the C64 it is fed from the VIC-II Φ0 output (VIC pin 17).
2RDYctrlReady. The VIC-II pulls this LOW through BA to stall the CPU on badlines.
3/IRQctrlInterrupt request from CIA1 and the VIC-II.
4/NMIctrlNon-maskable interrupt, from CIA2 (sheet).
5AECctrlAddress Enable Control. VIC-II takes it LOW to tri-state the CPU address bus during its own fetches.
6Vccpower+5 V logic supply.
7A0addrAddress bus bit 0.
8A1addrAddress bus bit 1.
9A2addrAddress bus bit 2.
10A3addrAddress bus bit 3.
11A4addrAddress bus bit 4.
12A5addrAddress bus bit 5.
13A6addrAddress bus bit 6.
14A7addrAddress bus bit 7.
15A8addrAddress bus bit 8.
16A9addrAddress bus bit 9.
17A10addrAddress bus bit 10.
18A11addrAddress bus bit 11.
19A12addrAddress bus bit 12.
20A13addrAddress bus bit 13.
21GNDground0 V.
22A14addrAddress bus bit 14.
23A15addrAddress bus bit 15.
24P5ioPort bit 5: Datasette motor control output (LOW = motor on).
25P4ioPort bit 4: Datasette sense input (play key down).
26P3ioPort bit 3: Datasette write output (cassette port pins E/5).
27P2ioProcessor port bit 2: /CHAREN, character ROM or I/O at $D000.
28P1ioProcessor port bit 1: /HIRAM, KERNAL ROM at $E000.
29P0ioProcessor port bit 0: /LORAM, BASIC ROM at $A000.
30D7dataData bus bit 7.
31D6dataData bus bit 6.
32D5dataData bus bit 5.
33D4dataData bus bit 4.
34D3dataData bus bit 3.
35D2dataData bus bit 2.
36D1dataData bus bit 1.
37D0dataData bus bit 0.
38R/WctrlRead/write from the CPU. HIGH = read, LOW = write.
39Φ2 OUTclockPhase 2 system clock out. Feeds the CIA (pin 25) and SID (pin 6) Φ2 inputs. UNVERIFIED
40/RESctrlReset. LOW at power-up, released HIGH so the CPU reads its reset vector.

Fitted in

Sources