8564 / 8566 VIC-IIe pinout

DIP-48. 40-column video, C64-compatible, plus C128 clocks and keyboard scan

8564 (NTSC) and 8566 (PAL). C64-compatible 40-column composite video, plus three keyboard-scan lines (K0-K2) and the Z80 (4 MHz), 1 MHz and 2 MHz clock lines the C128 needs. Vcc (pin 48) is +5 V. Fails as no or garbled 40-column display.

Open the interactive VIC-IIe pinout

Pins

PinNameTypeSignal
1DB6dataVIC-IIe data bus bit 6 (DB0-DB11 to color and screen RAM).
2DB5dataVIC-IIe data bus bit 5.
3DB4dataVIC-IIe data bus bit 4.
4DB3dataVIC-IIe data bus bit 3.
5DB2dataVIC-IIe data bus bit 2.
6DB1dataVIC-IIe data bus bit 1.
7DB0dataVIC-IIe data bus bit 0.
8/IRQctrlInterrupt request to the CPU.
9LPctrlLight pen: edge-triggered latch input.
10BActrlBus Available: LOW while the VIC needs the bus; gated to the CPU RDY.
11/DMARQSTctrlExternal DMA request input, pulled HIGH on the C128.
12AECctrlAddress Enable Control. Drops LOW when the VIC takes the bus.
13/CSctrlChip select from the MMU/PLA.
14R/WctrlRead/write from the CPU.
15/DMAACKctrlDMA acknowledge: the VIC answers an external DMA request. Not used in the C128 (N.C. on sheet 3).
16COLORvideoChroma output: color, burst and color of the display data.
17SYNCvideoComposite sync and luminance output.
181MHzclockThe 1 MHz system clock. All system bus activity is referenced to it.
19/RASctrlRow address strobe for the DRAM.
20/CASctrlColumn address strobe output for the DRAM.
21MUXctrlDRAM address multiplex control output.
22/I/O ACCctrlInput from the PLA: an I/O chip is being accessed, so stretch the clock to 1 MHz.
232MHzclockChanging system clock: 2 MHz in FAST mode when no VIC, DMA or I/O cycle is running, otherwise 1 MHz.
24VSSground0 V.
25Z80clockThe 4 MHz Z80 clock output.
26K0kbdExtended keyboard strobe bit 0.
27K1kbdExtended keyboard strobe bit 1.
28K2kbdExtended keyboard strobe bit 2.
29PH CLclockColor clock input: 14.31818 MHz NTSC.
30PH INclockDot clock input, the reference for all system clocks.
31A11addrVIC-IIe address bus bit 11 to the DRAM.
32A0addrAddress bit 0: multiplexed DRAM address out (A0 on the row, A8 on the column); address input latched on /RAS when the CPU reads or writes the VIC.
33A1addrAddress bit 1: multiplexed DRAM address out (A1 on the row, A9 on the column); address input latched on /RAS when the CPU reads or writes the VIC.
34A2addrAddress bit 2: multiplexed DRAM address out (A2 on the row, A10 on the column); address input latched on /RAS when the CPU reads or writes the VIC.
35A3addrAddress bit 3: multiplexed DRAM address out (A3 on the row, A11 on the column); address input latched on /RAS when the CPU reads or writes the VIC.
36A4addrAddress bit 4: multiplexed DRAM address out (A4 on the row, A12 on the column); address input latched on /RAS when the CPU reads or writes the VIC.
37A5addrAddress bit 5: multiplexed DRAM address out (A5 on the row, A13 on the column); address input latched on /RAS when the CPU reads or writes the VIC.
38A6addrVIC-IIe address bus bit 6 to the DRAM.
39A7addrVIC-IIe address bus bit 7 to the DRAM.
40A8addrVIC-IIe address bit 8, a static (non-multiplexed) output for character ROM and color RAM. DRAM row/column addresses use pins 32-37.
41A9addrVIC-IIe address bit 9, static output for character ROM and color RAM (not the DRAM path).
42A10addrVIC-IIe address bit 10, static output for character ROM and color RAM (not the DRAM path).
43DB11dataVIC-IIe data bus bit 11. UNVERIFIED
44DB10dataVIC-IIe data bus bit 10. UNVERIFIED
45DB9dataVIC-IIe data bus bit 9. UNVERIFIED
46DB8dataVIC-IIe data bus bit 8. UNVERIFIED
47DB7dataVIC-IIe data bus bit 7.
48Vccpower+5 V supply.

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