Yamaha V9938 MSX-Video display processor pinout

DIP-64. MSX2 video: TMS9918A-compatible VDP with bitmap modes, 512-color palette, RGB and composite out, 64-128 KB VRAM

Runs from a 21.47727 MHz crystal on XTAL1/XTAL2 and hands the Z80 its clock on CPUCLK (crystal / 6 = 3.58 MHz), so a dead V9938 or crystal can stop the whole machine, not just the picture. Ports $98 (VRAM), $99 (registers), $9A (palette), $9B (register pointer). Up to 128 KB VRAM on /CAS0 and /CAS1 (/CASX for 64 KB expansion VRAM), with 16K x 1, 16K x 4, 64K x 1 or 64K x 4 DRAM. Linear R, G, B and composite VIDEO out on pins 21-24 through external buffers. Unlike the TMS9918A, bit 0 of each bus is the LSB (CD0, RD0, AD0). Pin spacing is 1.778 mm: an ordinary 0.1 in socket will not fit.

Open the interactive V9938 pinout

Pins

PinNameTypeSignal
1GNDground0 V.
2/DHCLKclockDot clock for high resolution, open drain.
3/DLCLKclockDot clock for low resolution, open drain; can be an input (multi-VDP systems).
4/VDSctrlVRAM data select: LOW when the VRAM access is for display data, HIGH for other accesses.
5HSYNCvideoTri-level: HIGH non-HSYNC, MIDDLE HSYNC or non-color-burst period (output); LOW = HSYNC input.
6CSYNCvideoTri-level: composite sync output (HIGH levels); LOW = VSYNC input. UNVERIFIED
7BLEOvideoTri-level open drain: HIGH secondary field active, MIDDLE first field active, LOW blanking.
8CPUCLKclockClock out = crystal / 6; on an MSX2 this is the Z80 clock.
9/RESETctrlInitializes all V9938 circuits.
10/YSvideoSuperimpose switch: HIGH = V9938 output transparent (external video shows), LOW = V9938 output opaque.
11CBDRctrlColor bus direction: HIGH input, LOW output.
12C7ioColor bus bit 7 (MSB); mouse YB.
13C6ioColor bus bit 6; mouse YA.
14C5ioColor bus bit 5; mouse XB.
15C4ioColor bus bit 4; mouse XA.
16C3ioColor bus bit 3: color code out, or digitize input.
17C2ioColor bus bit 2.
18C1ioColor bus bit 1.
19C0ioColor bus bit 0 (LSB).
20GND DACground0 V for the video D/A converters.
21VIDEOvideoComposite video output (needs the external buffer).
22GvideoLinear green output.
23RvideoLinear red output.
24BvideoLinear blue output.
25/INTctrlInterrupt to the CPU, open drain (frame and line interrupts).
26/LPSioLight pen or mouse switch input: LOW = switch on.
27/LPDioLight pen detect or mouse switch input: LOW = light detected or switch on.
28MODE 1ctrlCPU interface mode select bit 1 (with MODE 0 picks one of the four VDP ports; normally Z80 A1).
29MODE 0ctrlCPU interface mode select bit 0 (normally Z80 A0).
30/CSWctrlCPU-to-VDP write strobe.
31/CSRctrlCPU-from-VDP read strobe.
32CD7dataCPU data bus bit 7 (MSB).
33VBBncBack bias (substrate) output. No connection.
34CD6dataCPU data bus bit 6.
35CD5dataCPU data bus bit 5.
36CD4dataCPU data bus bit 4.
37CD3dataCPU data bus bit 3.
38CD2dataCPU data bus bit 2.
39CD1dataCPU data bus bit 1.
40CD0dataCPU data bus bit 0 (LSB).
41RD0dataVRAM data bus bit 0 (LSB).
42RD1dataVRAM data bus bit 1.
43RD2dataVRAM data bus bit 2.
44RD3dataVRAM data bus bit 3.
45RD4dataVRAM data bus bit 4.
46RD5dataVRAM data bus bit 5.
47RD6dataVRAM data bus bit 6.
48RD7dataVRAM data bus bit 7 (MSB).
49AD0addrVRAM multiplexed address bit 0 (LSB).
50AD1addrVRAM address bit 1.
51AD2addrVRAM address bit 2.
52AD3addrVRAM address bit 3.
53AD4addrVRAM address bit 4.
54AD5addrVRAM address bit 5.
55AD6addrVRAM address bit 6.
56AD7addrVRAM address bit 7 (MSB).
57R/WctrlVRAM write strobe (LOW = write).
58VCCpower+5 V supply.
59/CASXctrlColumn address strobe for expansion VRAM.
60/CAS1ctrlColumn address strobe, VRAM second half. UNVERIFIED
61/CAS0ctrlColumn address strobe, VRAM first half. UNVERIFIED
62/RASctrlVRAM row address strobe.
63XTAL1clockCrystal, or external oscillator input.
64XTAL2clockCrystal (other side).

Fitted in

Sources