Yamaha V9938 MSX-Video display processor pinout
DIP-64. MSX2 video: TMS9918A-compatible VDP with bitmap modes, 512-color palette, RGB and composite out, 64-128 KB VRAM
Runs from a 21.47727 MHz crystal on XTAL1/XTAL2 and hands the Z80 its clock on CPUCLK (crystal / 6 = 3.58 MHz), so a dead V9938 or crystal can stop the whole machine, not just the picture. Ports $98 (VRAM), $99 (registers), $9A (palette), $9B (register pointer). Up to 128 KB VRAM on /CAS0 and /CAS1 (/CASX for 64 KB expansion VRAM), with 16K x 1, 16K x 4, 64K x 1 or 64K x 4 DRAM. Linear R, G, B and composite VIDEO out on pins 21-24 through external buffers. Unlike the TMS9918A, bit 0 of each bus is the LSB (CD0, RD0, AD0). Pin spacing is 1.778 mm: an ordinary 0.1 in socket will not fit.
Open the interactive V9938 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | GND | ground | 0 V. |
| 2 | /DHCLK | clock | Dot clock for high resolution, open drain. |
| 3 | /DLCLK | clock | Dot clock for low resolution, open drain; can be an input (multi-VDP systems). |
| 4 | /VDS | ctrl | VRAM data select: LOW when the VRAM access is for display data, HIGH for other accesses. |
| 5 | HSYNC | video | Tri-level: HIGH non-HSYNC, MIDDLE HSYNC or non-color-burst period (output); LOW = HSYNC input. |
| 6 | CSYNC | video | Tri-level: composite sync output (HIGH levels); LOW = VSYNC input. UNVERIFIED |
| 7 | BLEO | video | Tri-level open drain: HIGH secondary field active, MIDDLE first field active, LOW blanking. |
| 8 | CPUCLK | clock | Clock out = crystal / 6; on an MSX2 this is the Z80 clock. |
| 9 | /RESET | ctrl | Initializes all V9938 circuits. |
| 10 | /YS | video | Superimpose switch: HIGH = V9938 output transparent (external video shows), LOW = V9938 output opaque. |
| 11 | CBDR | ctrl | Color bus direction: HIGH input, LOW output. |
| 12 | C7 | io | Color bus bit 7 (MSB); mouse YB. |
| 13 | C6 | io | Color bus bit 6; mouse YA. |
| 14 | C5 | io | Color bus bit 5; mouse XB. |
| 15 | C4 | io | Color bus bit 4; mouse XA. |
| 16 | C3 | io | Color bus bit 3: color code out, or digitize input. |
| 17 | C2 | io | Color bus bit 2. |
| 18 | C1 | io | Color bus bit 1. |
| 19 | C0 | io | Color bus bit 0 (LSB). |
| 20 | GND DAC | ground | 0 V for the video D/A converters. |
| 21 | VIDEO | video | Composite video output (needs the external buffer). |
| 22 | G | video | Linear green output. |
| 23 | R | video | Linear red output. |
| 24 | B | video | Linear blue output. |
| 25 | /INT | ctrl | Interrupt to the CPU, open drain (frame and line interrupts). |
| 26 | /LPS | io | Light pen or mouse switch input: LOW = switch on. |
| 27 | /LPD | io | Light pen detect or mouse switch input: LOW = light detected or switch on. |
| 28 | MODE 1 | ctrl | CPU interface mode select bit 1 (with MODE 0 picks one of the four VDP ports; normally Z80 A1). |
| 29 | MODE 0 | ctrl | CPU interface mode select bit 0 (normally Z80 A0). |
| 30 | /CSW | ctrl | CPU-to-VDP write strobe. |
| 31 | /CSR | ctrl | CPU-from-VDP read strobe. |
| 32 | CD7 | data | CPU data bus bit 7 (MSB). |
| 33 | VBB | nc | Back bias (substrate) output. No connection. |
| 34 | CD6 | data | CPU data bus bit 6. |
| 35 | CD5 | data | CPU data bus bit 5. |
| 36 | CD4 | data | CPU data bus bit 4. |
| 37 | CD3 | data | CPU data bus bit 3. |
| 38 | CD2 | data | CPU data bus bit 2. |
| 39 | CD1 | data | CPU data bus bit 1. |
| 40 | CD0 | data | CPU data bus bit 0 (LSB). |
| 41 | RD0 | data | VRAM data bus bit 0 (LSB). |
| 42 | RD1 | data | VRAM data bus bit 1. |
| 43 | RD2 | data | VRAM data bus bit 2. |
| 44 | RD3 | data | VRAM data bus bit 3. |
| 45 | RD4 | data | VRAM data bus bit 4. |
| 46 | RD5 | data | VRAM data bus bit 5. |
| 47 | RD6 | data | VRAM data bus bit 6. |
| 48 | RD7 | data | VRAM data bus bit 7 (MSB). |
| 49 | AD0 | addr | VRAM multiplexed address bit 0 (LSB). |
| 50 | AD1 | addr | VRAM address bit 1. |
| 51 | AD2 | addr | VRAM address bit 2. |
| 52 | AD3 | addr | VRAM address bit 3. |
| 53 | AD4 | addr | VRAM address bit 4. |
| 54 | AD5 | addr | VRAM address bit 5. |
| 55 | AD6 | addr | VRAM address bit 6. |
| 56 | AD7 | addr | VRAM address bit 7 (MSB). |
| 57 | R/W | ctrl | VRAM write strobe (LOW = write). |
| 58 | VCC | power | +5 V supply. |
| 59 | /CASX | ctrl | Column address strobe for expansion VRAM. |
| 60 | /CAS1 | ctrl | Column address strobe, VRAM second half. UNVERIFIED |
| 61 | /CAS0 | ctrl | Column address strobe, VRAM first half. UNVERIFIED |
| 62 | /RAS | ctrl | VRAM row address strobe. |
| 63 | XTAL1 | clock | Crystal, or external oscillator input. |
| 64 | XTAL2 | clock | Crystal (other side). |
Fitted in
- MSX2 (generic) Varies by maker; 64-pin shrink DIP (SDIP, 1.778 mm pitch), usually beside the VRAM
Sources
- Yamaha V9938 MSX-Video Technical Data Book (ASCII / Nippon Gakki, Aug 1985), Part 2 sec. 2 pin assignments and functions, p. 114
- Yamaha V9938 MSX-Video Technical Data Book (ASCII / Nippon Gakki, Aug 1985), Part 2 sec. 2 pin functions (cont.), p. 115
- Yamaha V9938 MSX-Video Technical Data Book (ASCII / Nippon Gakki, Aug 1985), Part 2 sec. 1-4 MSX-Video circuit example (21.47727 MHz crystal, 128 KB VRAM), p. 113
- MSX2 Technical Handbook (ASCII, transcription on archive.org), ch. 1 sec. 2 MSX2 VRAM and VDP