TMS9918A / TMS9928A / TMS9929A video display processor pinout

DIP-40. Video display processor (VDP) with its own 16 KB DRAM bus. Composite out on 9918A; Y, R-Y, B-Y on 9928A/9929A.

The VDP drives the picture from up to 16 KB of DRAM on its own bus: AD0-AD7 carry the multiplexed address and write data with /RAS, /CAS and R/W, and RD0-RD7 bring read data back. It runs from a 10.738635 MHz crystal and divides it down for the color burst clock (pin 38, 9918A) and a GROM clock (pin 37). The 9928A (60 Hz) and 9929A (50 Hz) replace EXTVDP, COMVID and CPUCLK with B-Y, Y and R-Y outputs, so check the suffix before you swap. AD0, CD0 and RD0 are the MSBs. No picture or a garbled one points here and at the VRAM.

Open the interactive TMS9918A pinout

Pins

Pin	Name	Type	Signal
1	/RAS	ctrl	VRAM row address strobe to the DRAMs.
2	/CAS	ctrl	VRAM column address strobe to the DRAMs.
3	AD7	addr	VRAM address/data bit 7, the LSB. Wired to A0 of the DRAMs.
4	AD6	addr	VRAM address/data bit 6. Wired to A1 of the DRAMs.
5	AD5	addr	VRAM address/data bit 5.
6	AD4	addr	VRAM address/data bit 4.
7	AD3	addr	VRAM address/data bit 3.
8	AD2	addr	VRAM address/data bit 2.
9	AD1	addr	VRAM address/data bit 1.
10	AD0	addr	VRAM address/data bit 0, the MSB. Used only for write data, not for addressing.
11	R/W	ctrl	VRAM write strobe to the DRAM write-enable pins (low = write).
12	Vss	ground	0 V.
13	MODE	ctrl	CPU interface mode: selects data or register/address transfer. Usually a CPU address line.
14	/CSW	ctrl	CPU-to-VDP write strobe.
15	/CSR	ctrl	CPU-from-VDP read strobe.
16	/INT	ctrl	Interrupt output to the CPU side, at the end of each active frame when enabled.
17	CD7	data	CPU data bus bit 7, the LSB.
18	CD6	data	CPU data bus bit 6.
19	CD5	data	CPU data bus bit 5.
20	CD4	data	CPU data bus bit 4.
21	CD3	data	CPU data bus bit 3.
22	CD2	data	CPU data bus bit 2.
23	CD1	data	CPU data bus bit 1.
24	CD0	data	CPU data bus bit 0, the MSB.
25	RD7	data	VRAM read data bit 7, the LSB (from a DRAM data-out pin).
26	RD6	data	VRAM read data bit 6.
27	RD5	data	VRAM read data bit 5.
28	RD4	data	VRAM read data bit 4.
29	RD3	data	VRAM read data bit 3.
30	RD2	data	VRAM read data bit 2.
31	RD1	data	VRAM read data bit 1.
32	RD0	data	VRAM read data bit 0, the MSB.
33	Vcc	power	+5 V supply. The VDP is +5 V only.
34	/RESET	ctrl	RESET/SYNC, a three-level input: below 0.8 V resets the VDP; above 9 V it is the sync input for external video.
35	EXTVDP	video	TMS9918A: external VDP (external video) input. TMS9928A/9929A: B-Y color-difference output.
36	COMVID	video	TMS9918A: composite video output (needs an external pull-down resistor). TMS9928A/9929A: Y, luminance with composite sync.
37	GROMCLK	clock	Clock output = crystal / 24 (about 447 kHz with a 10.738635 MHz crystal).
38	CPUCLK	clock	TMS9918A: color burst clock = crystal / 3 (3.579545 MHz). TMS9928A/9929A: R-Y color-difference output.
39	XTAL2	clock	Crystal input (the other side of the crystal). If driven externally, both XTAL pins must be driven. Sams counts the 10.738635 MHz oscillator here. UNVERIFIED
40	XTAL1	clock	Crystal input, 10.738635 MHz. If driven externally, both XTAL pins must be driven. UNVERIFIED

Fitted in

TI-99/4A U100
TI-99/4
ColecoVision U9 (TMS9928A)
Coleco ADAM
MSX1 (generic) Varies by maker; TMS9918A (NTSC) or TMS9929A (PAL, also TMS9928A); 40-pin DIP beside the VRAM

TMS9918A / TMS9928A / TMS9929A video display processor pinout

Pins

Fitted in

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