8563 VDC pinout

DIP-48. 80-column RGBI video controller with its own video RAM

80-column video display controller with its own 16 or 64 KB video RAM (DA0-DA7 address and DD0-DD7 data). Outputs RGBI (R, G, B, I) to the 9-pin RGBI port. Two chip-select pins: pin 4 CS (active HIGH) and pin 7 /CS (active LOW); pins 5 and 6 are NC. Runs hot, low yield, and a known failure. Fails as no or garbled 80-column display.

Open the interactive VDC pinout

Pins

Pin	Name	Type	Signal
1	CCLK	clock	Character clock output.
2	/DCLK	clock	Video dot clock input (16 MHz oscillator on the C128).
3	HSYNC	video	Horizontal sync output (RGBI port).
4	CS	ctrl	Chip select, active HIGH. Pin 4 with pin 7 is the dual chip select.
5	NC	nc	No connection.
6	NC	nc	No connection.
7	/CS	ctrl	Chip select, active LOW. Pin 7 with pin 4 is the dual chip select.
8	/RS	ctrl	Register select. HIGH: read/write the selected data register. LOW: read status, write the address register.
9	R/W	ctrl	Read/write from the CPU.
10	D7	data	CPU data bus bit 7.
11	D6	data	CPU data bus bit 6.
12	VSS	ground	0 V.
13	D5	data	CPU data bus bit 5.
14	D4	data	CPU data bus bit 4.
15	D3	data	CPU data bus bit 3.
16	D2	data	CPU data bus bit 2.
17	D1	data	CPU data bus bit 1.
18	D0	data	CPU data bus bit 0.
19	DISPEN	ctrl	Display enable.
20	VSYNC	video	Vertical sync output (RGBI port).
21	DR/W	ctrl	Local display DRAM read/write.
22	INIT	ctrl	Active-LOW input that clears the internal control latches.
23	/RES	ctrl	Reset. Initializes the scan counters, not the control registers.
24	TEST	ground	Test input, tied to ground on the C128.
25	LPEN	ctrl	Light pen input.
26	DA0	addr	Local display DRAM address bus bit 0 (DD0-DD7 are the separate data bus).
27	DA1	addr	Local display DRAM address bus bit 1 (DD0-DD7 are the separate data bus).
28	DA2	addr	Local display DRAM address bus bit 2 (DD0-DD7 are the separate data bus).
29	DA3	addr	Local display DRAM address bus bit 3 (DD0-DD7 are the separate data bus).
30	DA4	addr	Local display DRAM address bus bit 4 (DD0-DD7 are the separate data bus).
31	DA5	addr	Local display DRAM address bus bit 5 (DD0-DD7 are the separate data bus).
32	DA6	addr	Local display DRAM address bus bit 6 (DD0-DD7 are the separate data bus).
33	DA7	addr	Local display DRAM address bus bit 7 (DD0-DD7 are the separate data bus).
34	DD0	data	Video RAM data bit 0.
35	DD1	data	Video RAM data bit 1.
36	DD2	data	Video RAM data bit 2.
37	VDD	power	+5 V DC supply.
38	DD3	data	Video RAM data bit 3.
39	DD4	data	Video RAM data bit 4.
40	DD5	data	Video RAM data bit 5.
41	DD6	data	Video RAM data bit 6.
42	DD7	data	Video RAM data bit 7.
43	I	video	Intensity pixel output (RGBI port pin 6).
44	B	video	Blue pixel output (RGBI port pin 5).
45	G	video	Green pixel output (RGBI port pin 4).
46	R	video	Red pixel output (RGBI port pin 3).
47	/RAS	ctrl	Row address strobe for the video RAM.
48	/CAS	ctrl	Column address strobe for the video RAM.

Fitted in

Commodore 128 U22

Sources

C128 Service Manual, 8563 pinout and pin description, p. 38