ZX81 ULA 2C184E / 2C210E pinout
DIP-40. Video sync, character access, keyboard, tape, NMI, ROM/RAM select
The ZX81 ULA (Ferranti 2C184E, later 2C210E) makes the picture and the CPU clock, reads the keyboard and the tape, selects the ROM and RAM and drives NMI for the display. It is a different chip from the Spectrum ULA. A dead ULA gives no display and no boot. Check +5 V at pin 40 and the 6.5 MHz resonator at pin 35 before replacing it.
Open the interactive ULA pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | A7' | addr | ROM-side address line A7' (direct to the ROM, to the CPU through 1 kohm). The ULA drives it with the character code during the refresh cycle of a display fetch. |
| 2 | A8' | addr | ROM-side address line A8'. Driven with the character code during display refresh cycles. |
| 3 | A2' | addr | ROM-side address line A2'. Driven with the character line counter during display refresh cycles. |
| 4 | A1' | addr | ROM-side address line A1'. Driven with the line counter during display refresh cycles. |
| 5 | A0' | addr | ROM-side address line A0'. Driven with the line counter during display refresh cycles. |
| 6 | /RD | ctrl | Read strobe, direct from the Z80. |
| 7 | /IORQ | ctrl | I/O request, direct from the Z80. |
| 8 | /WR | ctrl | Write strobe, direct from the Z80. |
| 9 | /MREQ | ctrl | Memory request, direct from the Z80. |
| 10 | /M1 | ctrl | Opcode fetch marker, direct from the Z80. |
| 11 | A14 | addr | CPU address bit 14 (direct). |
| 12 | /RAMCS | ctrl | RAM select, through 680 ohm (R2) to the RAM and edge pin A2. |
| 13 | /ROMCS | ctrl | ROM select (/MREQ OR A14), through 680 ohm (R28) to ROM pin 20 and edge pin B23. |
| 14 | /CLK | clock | CPU clock out, the inverse of the internal clock (6.5 MHz / 2). TR2 drives Z80 pin 6 from it. |
| 15 | /NMI | ctrl | NMI to the Z80, used to time the display. |
| 16 | TV/TAPE | video | Composite video and the tape (MIC) output on one pin; feeds the modulator. |
| 17 | /HALT | ctrl | HALT from the Z80. While a HALT runs the ULA loads no character data (Rea). |
| 18 | A15 | addr | CPU address bit 15 (direct). |
| 19 | D7 | data | Data bit 7, direct to the CPU. |
| 20 | TAPE IN | audio | Tape input from the EAR socket through C10 and R33 (4K7). |
| 21 | D6 | data | Data bit 6. |
| 22 | USA/UK | ctrl | TV standard strap: open on a UK machine, tied to 0 V on a US one. |
| 23 | D5 | data | Data bit 5. |
| 24 | D4 | data | Data bit 4. |
| 25 | KBD4 | kbd | Keyboard line 4 from the 5-way KB1 connector, pulled up by RP3. |
| 26 | D3 | data | Data bit 3. |
| 27 | KBD3 | kbd | Keyboard line 3. |
| 28 | D2 | data | Data bit 2. |
| 29 | KBD2 | kbd | Keyboard line 2. |
| 30 | D1 | data | Data bit 1. |
| 31 | KBD1 | kbd | Keyboard line 1. |
| 32 | D0 | data | Data bit 0. |
| 33 | KBD0 | kbd | Keyboard line 0. |
| 34 | 0V | ground | 0 V. |
| 35 | OSC | clock | Oscillator pin for the 6.5 MHz ceramic resonator X1 (CERAM OSC on the diagram). C6 100 pF, C7 47 pF and R4 18k complete the external network. |
| 36 | A3' | addr | ROM-side address line A3'. Driven with the character code during display refresh cycles; whether the ULA also reads it is not stated in the sources. UNVERIFIED |
| 37 | A4' | addr | ROM-side address line A4'. Character code during display refresh cycles. |
| 38 | A5' | addr | ROM-side address line A5'. Character code during display refresh cycles. |
| 39 | A6' | addr | ROM-side address line A6'. Character code during display refresh cycles. |
| 40 | +5V | power | +5 V supply. |
Fitted in
- ZX81 IC1
- Timex Sinclair 1000 IC1
