Spectrum ULA 5C102E / 6C001E pinout
DIP-40. Video, lower RAM timing and contention, keyboard, beeper, tape
The 16K/48K Spectrum ULA (Ferranti 5C102E on early boards, 6C001E later; Issue 4A and later boards need a 6C001E-7 or later) makes the video, the beeper and tape signal and the lower 16K RAM timing. When the CPU and the display both want the lower RAM it stops the CPU clock. It runs hot and is the most common failure. Check the 14 MHz crystal (pin 39) and +5 V (pins 13, 14) first.
Open the interactive ULA pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | /CAS | ctrl | Column address strobe to the lower 16K (4116s). |
| 2 | /WR | ctrl | Write strobe from the Z80. |
| 3 | /RD | ctrl | Read strobe from the Z80. |
| 4 | /WE | ctrl | DRAM write enable to the 4116s (DRAMWE on the diagram), decoded from /RD and /WR. |
| 5 | A0 | addr | Multiplexed lower-RAM address bit 0. The ULA drives the display address here; the CPU address arrives through IC3/IC4 and resistors R17-R23, and the ULA wins. |
| 6 | A1 | addr | Multiplexed lower-RAM address bit 1. |
| 7 | A2 | addr | Multiplexed lower-RAM address bit 2. |
| 8 | A3 | addr | Multiplexed lower-RAM address bit 3. |
| 9 | A4 | addr | Multiplexed lower-RAM address bit 4. |
| 10 | A5 | addr | Multiplexed lower-RAM address bit 5. |
| 11 | A6 | addr | Multiplexed lower-RAM address bit 6. |
| 12 | /INT | ctrl | Interrupt to the Z80 once per frame; the ROM scans the keyboard then. |
| 13 | +5V | power | +5 V (Vcc2 on the diagram). One of the two +5 V pins is fed through an RC low-pass (WoS). UNVERIFIED |
| 14 | +5V | power | +5 V (Vcc1 on the diagram). The service manual checks +5 V here. |
| 15 | U | video | Color difference signal U, to the LM1889 through a level shifter. |
| 16 | V | video | Color difference signal V, to the LM1889 through a level shifter. |
| 17 | /Y | video | Inverted luminance including sync. |
| 18 | D0 | data | Data bit 0, isolated from the CPU by R1-R8 so the ULA can read RAM while the CPU runs. |
| 19 | KB0 | kbd | Keyboard row input KB0 (ribbon KB1), pulled up by R65-R69 on the Issue 3 diagram. A pressed key pulls it LOW while its address line is LOW. UNVERIFIED |
| 20 | KB1 | kbd | Keyboard row input KB1. |
| 21 | D1 | data | Data bit 1. |
| 22 | D2 | data | Data bit 2. |
| 23 | KB2 | kbd | Keyboard row input KB2. |
| 24 | KB3 | kbd | Keyboard row input KB3. |
| 25 | D3 | data | Data bit 3 (port $FE write: MIC). |
| 26 | KB4 | kbd | Keyboard row input KB4. |
| 27 | D4 | data | Data bit 4 (port $FE write: speaker). |
| 28 | SOUND | audio | One analog pin for MIC out, EAR in and the beeper (MIC/TAPE on the diagram). Port $FE: write bit 3 = MIC, bit 4 = speaker; read bit 6 = EAR. |
| 29 | D5 | data | Data bit 5. |
| 30 | D6 | data | Data bit 6 (port $FE read: EAR). |
| 31 | D7 | data | Data bit 7. |
| 32 | CLK | clock | CPU clock out, 3.5 MHz (14 MHz / 4). The ULA stops it to hold the CPU off contended RAM; TR3 squares it to a full 5 V swing for Z80 pin 6. |
| 33 | /IOULA | ctrl | ULA port select (IO REQ on the diagram): /IORQ gated with A0 by TR6, so LOW only on an I/O cycle to an even port such as $FE. |
| 34 | /ROMCS | ctrl | ROM select to IC5 when A14 and A15 are LOW. R33 lets an add-on override it from edge pin 25A. |
| 35 | /RAS | ctrl | Row address strobe to the lower 16K (4116s). The upper 32K gets its strobes from IC23/IC24. |
| 36 | A14 | addr | CPU address bit 14. |
| 37 | A15 | addr | CPU address bit 15. The Issue 3 diagram misprints this pin as 27. |
| 38 | /MREQ | ctrl | Memory request from the Z80. |
| 39 | OSC | clock | Crystal input: X1, 14 MHz, other side to ground through a capacitor (WoS calls the pin Q). |
| 40 | GND | ground | 0 V. |
Fitted in
- ZX Spectrum 48K IC1
