Oric ULA HCS10017 pinout

DIP-40. Clock divider (12 MHz to 1 MHz), address decode (ROM, page-3 I/O, RAM), DRAM multiplexing and refresh, video generation (RGB, sync)

The Oric's custom chip. It takes 12 MHz on pin 7, gives the 6502 its 1 MHz clock on pin 14, decodes A8-A15 into /ROMSEL ($C000-$FFFF unless /MAP is low) and /I/O ($0300-$03FF), and shares the DRAM between the CPU and the video on alternate half-cycles through the external 74LS257 mux. It only reads the data bus, never drives it. RAS, CAS and the DRAM write are active high here and inverted by IC21 before the 4164s. No official datasheet exists; the pinout here is read from the Oric schematic and the diagnostic guides.

Open the interactive ULA pinout

Pins

Pin	Name	Type	Signal
1	MUX	ctrl	Select for the external 74LS257 address mux (IC8/IC20): CPU row address or ULA address.
2	MA5	addr	Multiplexed DRAM address bit 5 (column from A13 or video address), to the 74LS257.
3	MA4	addr	Multiplexed DRAM address bit 4, to the 74LS257.
4	MA3	addr	Multiplexed DRAM address bit 3, to the 74LS257.
5	D5	data	Data bus bit 5 (input only).
6	GND	ground	Ground, 0 V.
7	CLK	clock	12 MHz master clock from the XT1 oscillator (IC21 pin 2).
8	D0	data	Data bus bit 0.
9	CAS	ctrl	Column strobe, active high; IC21 pin 9 to 8 inverts it to 4164 /CAS (pin 15). Not asserted for ROM or page-3 accesses. UNVERIFIED
10	RAS	ctrl	Row strobe, active high; IC21 pin 11 to 10 inverts it to 4164 /RAS (pin 4). UNVERIFIED
11	D2	data	Data bus bit 2.
12	D3	data	Data bus bit 3.
13	D4	data	Data bus bit 4.
14	PHI OUT	clock	1 MHz system clock (12 MHz / 12), asymmetric, to 6502 PHI0 in (pin 37).
15	A11	addr	Address bit 11 from the 6502.
16	SYNC	video	Composite sync (no serrations), to IC22 and the RGB socket.
17	D1	data	Data bus bit 1.
18	D7	data	Data bus bit 7.
19	BLUE	video	Blue, TTL, to IC22.
20	GREEN	video	Green, TTL, to IC22.
21	RED	video	Red, TTL, to IC22.
22	A13	addr	Address bit 13.
23	/ROMSEL	ctrl	ROM select, low for $C000-$FFFF unless /MAP is low; to the ROM chip select.
24	VCC	power	+5 V supply (the wiki labels it VSS).
25	/I/O	ctrl	Low for $0300-$03FF: VIA CS2 (pin 23) and expansion pin 5.
26	/MAP	ctrl	From expansion pin 1 (2K2 pull-up). Low maps RAM in place of the ROM at $C000-$FFFF.
27	R/W IN	ctrl	6502 R/W (pin 34).
28	R/W OUT	ctrl	DRAM write, inverted by IC21 pin 3 to 4 to 4164 /W (pin 3). Forced to read during video fetches.
29	A14	addr	Address bit 14.
30	A15	addr	Address bit 15.
31	A10	addr	Address bit 10.
32	A8	addr	Address bit 8.
33	A9	addr	Address bit 9.
34	D6	data	Data bus bit 6.
35	A12	addr	Address bit 12. UNVERIFIED
36	MA1	addr	Multiplexed DRAM address bit 1, to the 74LS257.
37	MA2	addr	Multiplexed DRAM address bit 2, to the 74LS257.
38	MA0	addr	Multiplexed DRAM address bit 0, to the 74LS257.
39	MA7	addr	Multiplexed DRAM address bit 7, to the 74LS257.
40	MA6	addr	Multiplexed DRAM address bit 6, to the 74LS257.

Fitted in

Oric-1 IC7
Oric Atmos IC7 (same numbering per the Oric/Atmos checklist; verify)

Oric ULA HCS10017 pinout

Pins

Fitted in

Sources