TMS9900 16-bit CPU pinout
DIP-64. 16-bit CPU at 3 MHz. Needs -5 V, +5 V and +12 V, plus a 4-phase clock.
The 16-bit CPU. It needs three rails (-5 V on pin 1, +5 V on pins 2 and 59, +12 V on pin 27) and a four-phase 12 V clock from the TIM9904. The 9900 numbers its buses MSB first: A0 and D0 are the most significant bits. A dead 9900 or a missing clock gives a dead console and no title screen. Check the rails and the clocks on pins 8, 9, 25 and 28 before you swap the big 64-pin chip.
Open the interactive TMS9900 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | Vbb | power | -5 V supply (Vbb). The 9900 needs all three rails. |
| 2 | Vcc | power | +5 V supply. Pins 2 and 59 must be connected in parallel. |
| 3 | WAIT | ctrl | Wait. High when the CPU has entered a wait state because READY was low. |
| 4 | /LOAD | ctrl | Load: non-maskable interrupt (vectors at $FFFC and $FFFE). Brought out on I/O port pin 13. |
| 5 | HOLDA | ctrl | Hold acknowledge. High = the CPU has floated its address, data and memory-control lines. |
| 6 | /RESET | ctrl | Reset input, from the TIM9904 flip-flop output (FFQ, pin 4). LOW at power-on, then HIGH to run. |
| 7 | IAQ | ctrl | Instruction acquisition. High while an instruction is fetched. |
| 8 | PHI1 | clock | Clock phase 1 (MOS level) from TIM9904 pin 12. |
| 9 | PHI2 | clock | Clock phase 2 from TIM9904 pin 11. |
| 10 | A14 | addr | Address bus bit 14, the least significant (the 9900 numbers A0 as the MSB). |
| 11 | A13 | addr | Address bus bit 13. |
| 12 | A12 | addr | Address bus bit 12. |
| 13 | A11 | addr | Address bus bit 11. |
| 14 | A10 | addr | Address bus bit 10. |
| 15 | A9 | addr | Address bus bit 9. |
| 16 | A8 | addr | Address bus bit 8. |
| 17 | A7 | addr | Address bus bit 7. |
| 18 | A6 | addr | Address bus bit 6. |
| 19 | A5 | addr | Address bus bit 5. |
| 20 | A4 | addr | Address bus bit 4. |
| 21 | A3 | addr | Address bus bit 3. |
| 22 | A2 | addr | Address bus bit 2. |
| 23 | A1 | addr | Address bus bit 1. |
| 24 | A0 | addr | Address bus bit 0, the most significant. |
| 25 | PHI4 | clock | Clock phase 4 from TIM9904 pin 9. |
| 26 | Vss | ground | 0 V. Pins 26 and 40 must be connected in parallel. |
| 27 | Vdd | power | +12 V supply (Vdd). |
| 28 | PHI3 | clock | Clock phase 3 from TIM9904 pin 8. |
| 29 | DBIN | ctrl | Data bus in. High while the CPU reads (its output buffers are off). |
| 30 | CRUOUT | io | CRU serial data out, sampled when CRUCLK is high. |
| 31 | CRUIN | io | CRU serial data in, sampled for STCR and TB. |
| 32 | /INTREQ | ctrl | Interrupt request from the 9901. Low = interrupt; the CPU then reads IC0-IC3. |
| 33 | IC3 | ctrl | Interrupt code bit 3, the LSB. |
| 34 | IC2 | ctrl | Interrupt code bit 2. |
| 35 | IC1 | ctrl | Interrupt code bit 1. |
| 36 | IC0 | ctrl | Interrupt code bit 0, the MSB. |
| 37 | NC | nc | No internal connection. |
| 38 | NC | nc | No internal connection. |
| 39 | NC | nc | No internal connection. |
| 40 | Vss | ground | 0 V (second ground pin). |
| 41 | D0 | data | Data bus bit 0, the most significant. |
| 42 | D1 | data | Data bus bit 1. |
| 43 | D2 | data | Data bus bit 2. |
| 44 | D3 | data | Data bus bit 3. |
| 45 | D4 | data | Data bus bit 4. |
| 46 | D5 | data | Data bus bit 5. |
| 47 | D6 | data | Data bus bit 6. |
| 48 | D7 | data | Data bus bit 7. |
| 49 | D8 | data | Data bus bit 8. |
| 50 | D9 | data | Data bus bit 9. |
| 51 | D10 | data | Data bus bit 10. |
| 52 | D11 | data | Data bus bit 11. |
| 53 | D12 | data | Data bus bit 12. |
| 54 | D13 | data | Data bus bit 13. |
| 55 | D14 | data | Data bus bit 14. |
| 56 | D15 | data | Data bus bit 15, the least significant. |
| 57 | NC | nc | No internal connection. |
| 58 | NC | nc | No internal connection. |
| 59 | Vcc | power | +5 V supply (second pin). |
| 60 | CRUCLK | io | CRU clock. High = valid data on CRUOUT (or an external instruction code on A0-A2). |
| 61 | /WE | ctrl | Write enable. LOW = write data is on the bus. |
| 62 | READY | ctrl | Ready. High = memory ready next cycle; low = the CPU waits. |
| 63 | /MEMEN | ctrl | Memory enable. LOW = the address bus holds a memory address. |
| 64 | /HOLD | ctrl | Hold request. LOW asks the CPU to release the bus (DMA). |