7360 / 8360 TED pinout
DIP-48. Video, sound, DRAM controller, MMU, keyboard scan
The heart of the 264 series: 121-color video, 2-voice sound, DRAM controller (/RAS, /CAS, MUX), ROM chip-selects (a simple MMU), timers and keyboard scan (K0-K7). Runs hot and is the number one failure. Replacements are a TED from another 264-series board or the FPGATED below, so socket it and fit a heatsink.
Open the interactive TED pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | A2 | addr | Address bus bit 2 (input for register access, output during DMA/refresh). |
| 2 | A1 | addr | Address bus bit 1. |
| 3 | A0 | addr | Address bus bit 0. |
| 4 | VCC | power | +5 V supply. TED draws a lot; expect the body to be hot. |
| 5 | /CS0 | ctrl | Low ROM chip-select, active for $8000-$BFFF (BASIC ROM). Active LOW (C16 SM). |
| 6 | /CS1 | ctrl | High ROM chip-select, active for $C000-$FFFF (KERNAL ROM). Active LOW (C16 SM). |
| 7 | R/W | ctrl | Read/Write input from the CPU. TED also pulls it HIGH during its own fetches (open-source output), so it is an input and an output. |
| 8 | /IRQ | ctrl | Interrupt to the CPU, open drain: raster compare and timers 1-3. |
| 9 | MUX | ctrl | DRAM row/column address multiplex control to the 4164s. |
| 10 | /RAS | ctrl | DRAM Row Address Strobe. |
| 11 | /CAS | ctrl | DRAM Column Address Strobe. |
| 12 | Φ OUT | clock | System clock out to 7501 pin 1. Doubles during blanking: 0.89 / 1.79 MHz NTSC (1.788 MHz), 0.88 / 1.77 MHz PAL (1.768 MHz). |
| 13 | COLOR | video | Chroma output, open source; terminated with 1 kΩ to ground. |
| 14 | Φ IN | clock | Master clock in: 14.31818 MHz (NTSC) or 17.734475 MHz (PAL), ±70 ppm. |
| 15 | K0 | kbd | Keyboard latch input 0 (pulled up by TED). Driving it to 10 V triggers a test mode. |
| 16 | K1 | kbd | Keyboard latch input 1 (pulled up by TED). Driving it to 10 V forces NTSC timing. |
| 17 | K2 | kbd | Keyboard row input 2. |
| 18 | K3 | kbd | Keyboard row input 3. |
| 19 | K4 | kbd | Keyboard row input 4. |
| 20 | K5 | kbd | Keyboard row input 5. |
| 21 | K6 | kbd | Keyboard row input 6. |
| 22 | K7 | kbd | Keyboard row input 7. |
| 23 | LUM | video | Composite sync + luminance, open drain with a 1 kΩ pull-up. |
| 24 | VSS | ground | 0 V. |
| 25 | DB0 | data | Data bus bit 0. |
| 26 | DB1 | data | Data bus bit 1. |
| 27 | DB2 | data | Data bus bit 2. |
| 28 | DB3 | data | Data bus bit 3. |
| 29 | DB4 | data | Data bus bit 4. |
| 30 | DB5 | data | Data bus bit 5. |
| 31 | DB6 | data | Data bus bit 6. |
| 32 | DB7 | data | Data bus bit 7. |
| 33 | SND | audio | Sound output (2 voices: tone + tone/noise). |
| 34 | BA | ctrl | Bus Available: goes LOW before TED takes the bus. Drives CPU RDY. |
| 35 | AEC | ctrl | Address Enable Control to CPU pin 4. |
| 36 | A15 | addr | Address bus bit 15. |
| 37 | A14 | addr | Address bus bit 14. |
| 38 | A13 | addr | Address bus bit 13. |
| 39 | A12 | addr | Address bus bit 12. |
| 40 | A11 | addr | Address bus bit 11. |
| 41 | A10 | addr | Address bus bit 10. |
| 42 | A9 | addr | Address bus bit 9. |
| 43 | A8 | addr | Address bus bit 8. |
| 44 | A7 | addr | Address bus bit 7. |
| 45 | A6 | addr | Address bus bit 6. |
| 46 | A5 | addr | Address bus bit 5. |
| 47 | A4 | addr | Address bus bit 4. |
| 48 | A3 | addr | Address bus bit 3. |