MC6883 synchronous address multiplexer pinout

DIP-40. Makes all clocks from the 14.31818 MHz crystal, the DRAM strobes and address multiplex, and the device selects. Used in the CoCo 1 and 2 and the Dragon 32 and 64.

The SAM makes every clock the CoCo needs, the DRAM /RAS and /CAS strobes with the MA0 to MA7 multiplex, and the device selects S0 to S2 for the ROM, I/O and VDG. It also takes the register writes at $FFC0 to $FFDF. A bad SAM looks like a dead machine: it makes the clocks. It runs warm.

Open the interactive SAM pinout

Pins

Pin	Name	Type	Signal
1	A11	addr	CPU address bit 11 in.
2	A10	addr	CPU address bit 10 in.
3	A9	addr	CPU address bit 9 in.
4	A8	addr	CPU address bit 8 in.
5	OSCin	clock	Crystal input for the master oscillator (crystal between pins 5 and 6).
6	OSCout	clock	Crystal output, through 1.5 kΩ to the crystal.
7	VClk	clock	VDG clock out (crystal / 4). Pulled LOW, it resets the SAM.
8	DA0	addr	Display address bit 0 from the VDG. Clocks the SAM internal video address counter.
9	/HS	ctrl	Horizontal sync from VDG pin 38. Its falling edge starts eight DRAM refresh cycles.
10	/WE	ctrl	DRAM write enable. Active LOW.
11	/CAS	ctrl	DRAM column address strobe. Active LOW.
12	/RAS0	ctrl	Row address strobe for DRAM bank 0.
13	Q	clock	Q (quadrature) clock to the 6809E pin 35.
14	E	clock	E (enable) clock to the 6809E pin 34 and the PIAs. Crystal / 16 at the slow MPU rate (0.89 MHz with 14.31818 MHz) or crystal / 8 at the fast rate (1.79 MHz), set by the SAM rate bits.
15	R/W	ctrl	Read / write from the 6809E. Enables writes to the SAM register, the DRAM (/WE) and device select 0.
16	A0	addr	CPU address bit 0 in.
17	A1	addr	CPU address bit 1 in.
18	A2	addr	CPU address bit 2 in.
19	A3	addr	CPU address bit 3 in.
20	GND	ground	Ground.
21	A4	addr	CPU address bit 4 in.
22	A5	addr	CPU address bit 5 in.
23	A6	addr	CPU address bit 6 in.
24	A7	addr	CPU address bit 7 in.
25	S2	ctrl	Device select bit 2 from the SAM decode.
26	S1	ctrl	Device select bit 1 from the SAM decode.
27	S0	ctrl	Device select bit 0 from the SAM decode.
28	Z0	addr	Multiplexed DRAM address bit 0 (MA0 on the Tandy schematics).
29	Z1	addr	Multiplexed DRAM address bit 1 (MA1 on the Tandy schematics).
30	Z2	addr	Multiplexed DRAM address bit 2 (MA2 on the Tandy schematics).
31	Z3	addr	Multiplexed DRAM address bit 3 (MA3 on the Tandy schematics).
32	Z4	addr	Multiplexed DRAM address bit 4 (MA4 on the Tandy schematics).
33	Z5	addr	Multiplexed DRAM address bit 5 (MA5 on the Tandy schematics).
34	Z6	addr	Multiplexed DRAM address bit 6 (MA6 on the Tandy schematics).
35	Z7	addr	Multiplexed DRAM address bit 7 (MA7 on the Tandy schematics). Doubles as /RAS1 for bank 1 with 4K and 16K RAM.
36	A15	addr	CPU address bit 15 in. Top bit of the 64K map.
37	A14	addr	CPU address bit 14 in.
38	A13	addr	CPU address bit 13 in.
39	A12	addr	CPU address bit 12 in.
40	Vcc	power	+5 V supply, under 230 mA.

MC6883 synchronous address multiplexer pinout

Pins

Fitted in

Sources