TMS4732 console ROM (4K x 8) pinout
DIP-24. Console ROM at $0000-$1FFF: two 4 KB chips, one per byte of the 16-bit word.
The 8 KB console ROM is two TMS4732 4K x 8 mask ROMs on the 16-bit bus: U610 feeds D0-D7 and U611 feeds D8-D15. Both chip selects are low to enable on the TI. The part is pin-compatible with the TMS2532 EPROM, which Sams lists as a substitute, but on a 2532 pins 18, 20 and 21 are /PD-PGM, Vpp and A11, so check the socket before fitting one. A bad ROM gives no title screen or a garbled boot.
Open the interactive TMS4732 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | A7 | addr | Address input 7 (A0 = LSB). |
| 2 | A6 | addr | Address input 6. |
| 3 | A5 | addr | Address input 5. |
| 4 | A4 | addr | Address input 4. |
| 5 | A3 | addr | Address input 3. |
| 6 | A2 | addr | Address input 2. |
| 7 | A1 | addr | Address input 1. |
| 8 | A0 | addr | Address input 0, the LSB. |
| 9 | Q1 | data | Data out 1, the LSB. Three-state. |
| 10 | Q2 | data | Data out 2. |
| 11 | Q3 | data | Data out 3. |
| 12 | Vss | ground | 0 V. |
| 13 | Q4 | data | Data out 4. |
| 14 | Q5 | data | Data out 5. |
| 15 | Q6 | data | Data out 6. |
| 16 | Q7 | data | Data out 7. |
| 17 | Q8 | data | Data out 8, the MSB. |
| 18 | A11 | addr | Address input 11, the MSB. |
| 19 | A10 | addr | Address input 10. |
| 20 | /S2 | ctrl | Chip enable/power down or second chip select; polarity is set in the mask. Low enables the TI console ROMs. |
| 21 | /S1 | ctrl | Chip select; polarity is set in the mask. Low enables the TI console ROMs. |
| 22 | A9 | addr | Address input 9. |
| 23 | A8 | addr | Address input 8. |
| 24 | Vcc | power | +5 V supply. |