8253-5 programmable interval timer pinout
DIP-24. Three 16-bit counters: time-of-day tick, DRAM refresh pacing and the speaker tone.
Three counters at port $40, each clocked at 1.19 MHz on the PC (PCLK divided by 2). Counter 0 makes IRQ0, the time-of-day tick. Counter 1 requests DRAM refresh on DMA channel 0. Counter 2, gated by PPI PB0, drives the speaker and, on the 5150, cassette data out. On the 5150 (U34) GATE0 and GATE1 are tied to +5 V and all three CLK pins share the 1.19 MHz clock. A dead timer gives the one-long-one-short beep and failing memory. PCjr (ZM23): no DMA refresh. Counter 1 helps the BIOS deserialize keyboard data, or counts timer 0 overflows during diskette I/O; port $A0 bit 5 picks its clock.
Open the interactive 8253 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | D7 | data | Data bus bit 7. |
| 2 | D6 | data | Data bus bit 6. |
| 3 | D5 | data | Data bus bit 5. |
| 4 | D4 | data | Data bus bit 4. |
| 5 | D3 | data | Data bus bit 3. |
| 6 | D2 | data | Data bus bit 2. |
| 7 | D1 | data | Data bus bit 1. |
| 8 | D0 | data | Data bus bit 0. |
| 9 | CLK0 | clock | Counter 0 clock. PC: 1.19 MHz. PCjr: 1.1925 MHz from ZM34 (74LS112) pin 9, shared with CLK2. |
| 10 | OUT0 | ctrl | Counter 0 output. PC: IRQ0, the timer interrupt. |
| 11 | GATE0 | ctrl | Counter 0 gate. PCjr: tied to +5 V. |
| 12 | GND | ground | Ground. |
| 13 | OUT1 | ctrl | Counter 1 output. PC: clocks the refresh-request flip-flop that drives DMA DREQ0. PCjr: not connected; the BIOS reads counter 1 to time keyboard bits. |
| 14 | GATE1 | ctrl | Counter 1 gate. PCjr: tied to +5 V. |
| 15 | CLK1 | clock | Counter 1 clock. PC: 1.19 MHz. PCjr: 1.1925 MHz, or timer 0 OUT0 when port $A0 bit 5 is 1. |
| 16 | GATE2 | ctrl | Counter 2 gate. PC: from PPI PB0 (timer 2 gate speaker). PCjr: from 8255 PB0. |
| 17 | OUT2 | ctrl | Counter 2 output. PC: speaker tone (gated with PPI PB1), read back on PPI PC5; on the 5150 also cassette data out. PCjr: speaker tone, gated with 8255 PB1 in ZM1 (74LS08); read back on 8255 PC5; also cassette data out and the IR receiver test. |
| 18 | CLK2 | clock | Counter 2 clock. PC: 1.19 MHz. PCjr: 1.1925 MHz, as CLK0. |
| 19 | A0 | addr | Address bit 0. With A1 selects counter 0, 1, 2 or the control word. |
| 20 | A1 | addr | Address bit 1. |
| 21 | /CS | ctrl | Chip select, active LOW. PC: ports $40 to $43. |
| 22 | /RD | ctrl | Read strobe, active LOW. |
| 23 | /WR | ctrl | Write strobe, active LOW. |
| 24 | VCC | power | +5 V supply. |
Fitted in
Sources
- Intel 8253/8253-5 data sheet, 1983 Microprocessors and Peripherals Handbook p. 6-139
- IBM PC Technical Reference (Apr 1983), 16/64K system board logic diagram, sheet 8 (U34 8253)
- IBM PC Technical Reference (Apr 1983), speaker drive and timer use, p. 1-23
- PCjr Technical Reference (Nov 1983), 8253-5 channel use, p. 2-6
- PCjr Technical Reference (Nov 1983), port $A0 bit 5 (timer 1 clock select), p. 2-35
- PCjr Technical Reference (Nov 1983), system board logic diagram sheet 9 (8255A-5 at ZM22, 8253-5 at ZM23), p. B-11