8259A programmable interrupt controller pinout
DIP-28. Eight interrupt inputs (IRQ0 to IRQ7), priority logic and the vector for the 8088.
Takes eight interrupt requests, masks them, and passes the highest-priority one to the 8088 INTR pin. IRQ0 is the timer and IRQ1 the keyboard; IRQ2 to IRQ7 come from the I/O channel. It sits at port $20 (U2 on the 5150). The POST tests it early, so a dead chip gives the one-long-one-short beep. PCjr (ZM32): also at $20, but the IRQ use differs (serial, modem, vertical retrace, diskette).
Open the interactive 8259A pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | /CS | ctrl | Chip select, active LOW. Enables /RD and /WR. /INTA works without it. |
| 2 | /WR | ctrl | Write strobe, active LOW. Loads the command words. |
| 3 | /RD | ctrl | Read strobe, active LOW. Reads IRR, ISR or the mask. |
| 4 | D7 | data | Data bus bit 7. |
| 5 | D6 | data | Data bus bit 6. |
| 6 | D5 | data | Data bus bit 5. |
| 7 | D4 | data | Data bus bit 4. |
| 8 | D3 | data | Data bus bit 3. |
| 9 | D2 | data | Data bus bit 2. |
| 10 | D1 | data | Data bus bit 1. |
| 11 | D0 | data | Data bus bit 0. |
| 12 | CAS0 | ctrl | Cascade line 0. Master output, slave input. Unused with one 8259A. |
| 13 | CAS1 | ctrl | Cascade line 1. |
| 14 | GND | ground | Ground. |
| 15 | CAS2 | ctrl | Cascade line 2. |
| 16 | /SP/EN | ctrl | Slave program input (HIGH = master) or, in buffered mode, transceiver enable output. |
| 17 | INT | ctrl | Interrupt output, active HIGH, to the 8088 INTR pin (18). |
| 18 | IR0 | ctrl | Interrupt request 0, rising edge or level. PC: system timer, 8253 OUT0. PCjr: timer (8253 OUT0). |
| 19 | IR1 | ctrl | Interrupt request 1, rising edge or level. PC: keyboard. PCjr: I/O channel, reserved. |
| 20 | IR2 | ctrl | Interrupt request 2, rising edge or level. PC: reserved (I/O channel B4). PCjr: I/O channel. |
| 21 | IR3 | ctrl | Interrupt request 3, rising edge or level. PC: secondary asynchronous (COM2), SDLC or BSC (I/O channel B25). PCjr: serial port (RS-232C). |
| 22 | IR4 | ctrl | Interrupt request 4, rising edge or level. PC: primary asynchronous (COM1) or SDLC (B24). PCjr: internal modem. |
| 23 | IR5 | ctrl | Interrupt request 5, rising edge or level. PC: fixed disk on the XT (B23). PCjr: vertical retrace from the video gate array. |
| 24 | IR6 | ctrl | Interrupt request 6, rising edge or level. PC: diskette controller (B22). PCjr: diskette adapter. |
| 25 | IR7 | ctrl | Interrupt request 7, rising edge or level. PC: printer (B21). PCjr: I/O channel (parallel printer). |
| 26 | /INTA | ctrl | Interrupt acknowledge, active LOW, from the 8288. The pulses put the vector on the data bus. PCjr: there is no 8288; in minimum mode the 8088 makes /INTA itself (8088 pin 24). |
| 27 | A0 | addr | Address bit 0. Selects between the command and status words. |
| 28 | VCC | power | +5 V supply. |
Fitted in
Sources
- Intel 8259A data sheet, 1983 Microprocessors and Peripherals Handbook p. 2-120
- Intel 8259A data sheet, order 231468-003 (MIT copy)
- IBM PC Technical Reference (Apr 1983), 8088 hardware interrupt listing (PDF p. 19)
- PCjr Technical Reference (Nov 1983), 8259A interrupt controller and IRQ list, p. 2-15
- PCjr Technical Reference (Nov 1983), system board logic diagram sheet 1 (8259A at ZM32), p. B-3