8722 MMU pinout

DIP-48. Memory management: ROM/RAM banks, common areas, CPU select

Memory management unit. Chooses which CPU (8502 or Z80) drives the bus, the ROM/RAM bank mapping across $0000-$FFFF, and the common areas. Outputs translated addresses TA8-TA15. Pins 22 and 23 are multiplexed (A4/A5 and A6/A7). Fails: dead in 64 or 128 mode, or bad banking. Verify the pinout against the datasheet before use: the sheet calls the chip reconstructed in places.

Open the interactive MMU pinout

Pins

Pin	Name	Type	Signal
1	VDD	power	+5 V supply.
2	/RESET	ctrl	Reset.
3	TA15	addr	Translated address bit 15.
4	TA14	addr	Translated address bit 14.
5	TA13	addr	Translated address bit 13.
6	TA12	addr	Translated address bit 12.
7	TA11	addr	Translated address bit 11.
8	TA10	addr	Translated address bit 10.
9	TA9	addr	Translated address bit 9.
10	TA8	addr	Translated address bit 8.
11	/CAS1	ctrl	Column address strobe, bank 1.
12	/CAS0	ctrl	Column address strobe, bank 0.
13	I/O SEL	ctrl	I/O select.
14	MS1	ctrl	Memory select bit 1 (bank mapping).
15	MS0	ctrl	Memory select bit 0 (bank mapping).
16	AEC	ctrl	Address Enable Control from the VIC.
17	MUX	ctrl	MUX from VIC-IIe pin 21: the DRAM row/column multiplex signal, also clocking MMU sections.
18	A0	addr	CPU address bit 0.
19	A1	addr	CPU address bit 1.
20	A2	addr	CPU address bit 2.
21	A3	addr	CPU address bit 3.
22	A4/5	addr	Multiplexed: CPU address bit 4 or 5 (see the pin note: pins 22 and 23 are shared).
23	A6/7	addr	Multiplexed: CPU address bit 6 or 7 (see the pin note).
24	A8	addr	CPU address bit 8.
25	A9	addr	CPU address bit 9.
26	A10	addr	CPU address bit 10.
27	A11	addr	CPU address bit 11.
28	A12	addr	CPU address bit 12.
29	A13	addr	CPU address bit 13.
30	A14	addr	CPU address bit 14.
31	A15	addr	CPU address bit 15.
32	R/W	ctrl	Read/write from the CPU.
33	PHI0	clock	Phase 0 system clock input, from the VIC clock path.
34	VSS	ground	0 V.
35	D0	data	Data bus bit 0.
36	D1	data	Data bus bit 1.
37	D2	data	Data bus bit 2.
38	D3	data	Data bus bit 3.
39	D4	data	Data bus bit 4.
40	D5	data	Data bus bit 5.
41	D6	data	Data bus bit 6.
42	D7	data	Data bus bit 7.
43	/Z80EN	ctrl	Enables the Z80 (LOW when the Z80 is selected).
44	FSDIR	ctrl	Fast serial direction: in output mode sets the data direction of the fast serial disk interface.
45	/GAME	ctrl	C64 mode: senses the expansion-port GAME line. C128 mode: color-RAM bank control.
46	/EXROM	ctrl	C64 mode: senses the expansion-port EXROM line. C128 mode: expansion control line.
47	128/64	ctrl	Mode output: LOW = C64 mode, HIGH = C128 mode.
48	SENSE40	ctrl	Senses the 40/80 DISPLAY key (input mode). Output mode unused.

Fitted in

Commodore 128 U7

Sources

C128 Service Manual, 8722 MMU pinout and pin description, p. 27