TMC0430 GROM (graphics ROM) pinout
DIP-16. 6 KB serial ROM for TI BASIC, the title screen and cartridge code.
A P-channel ROM holding 6144 bytes, read one byte at a time through an auto-incrementing address counter. All GROMs share the data bus, /GS, M0, M1 and the clock; each has a fixed page number and only the matching one drives data. The console has three (U500-U502, Sams part numbers CD2155NL, CD2156NL, CD2157NL); a cartridge can add five more through the cartridge port. It needs +5 V (pin 9), -5 V (pin 14) and the 447 kHz VDP clock (pin 13). The TI debug list checks GROM select pin 10, ready pin 15 and clock pin 13.
Open the interactive GROM pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | D7 | data | Data bit 7, the LSB (TI numbering). |
| 2 | D6 | data | Data bit 6. |
| 3 | D5 | data | Data bit 5. |
| 4 | D4 | data | Data bit 4. |
| 5 | D3 | data | Data bit 3. |
| 6 | D2 | data | Data bit 2. |
| 7 | D1 | data | Data bit 1. |
| 8 | D0 | data | Data bit 0, the MSB. |
| 9 | Vcc | power | +5 V supply. |
| 10 | /GS | ctrl | GROM select (chip enable). All GROMs share it. On a data read only the GROM whose page number matches the address drives the bus; on an address read every GROM puts out the address byte. |
| 11 | M0 | ctrl | Mode 0: data (0) or address (1) register. On the TI: from A14. |
| 12 | M1 | ctrl | Mode 1: write (0) or read (1). On the TI: from DBIN. |
| 13 | GRCLK | clock | GROM clock, nominal 500 kHz. On the TI: the VDP GROMCLK (about 447 kHz) with a 1 k pull-up. |
| 14 | Vdd | power | -5 V supply (P-channel part). |
| 15 | GREADY | ctrl | GROM ready. Normally low; high once the GROM has taken or placed its byte. Feeds the CPU READY. |
| 16 | Vss | ground | Vss reference. On the 99/4A this node is shared by all GROMs, brought out on cartridge port pin 33 ("GROM VSS") and returned to ground through CR500 and R501. |