GIME TCC1014 (Advanced Color Video Chip) pinout
PLCC-68. CoCo 3 video, 512 K MMU, DRAM control, clocks and interrupts. Replaces the VDG and SAM.
The GIME replaces the 6847 and the 6883 on the CoCo 3. It runs from a 28.63636 MHz crystal and supplies E and Q, the DRAM strobes and the multiplexed address, the MMU for 128 or 512 KB, the hi-res and 16-color video (RGB and composite), the device selects and the interrupts. Almost every CoCo 3 fault routes through it, so check its clocks and supply first. It is a 68-pin PLCC (IC6), numbered counter-clockwise from the index corner.
Open the interactive GIME pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | VSS | ground | Ground. |
| 2 | EXTAL | clock | Crystal input. X1 is 28.63636 MHz on the NTSC board. |
| 3 | XTAL | clock | Crystal output. |
| 4 | /RAS | ctrl | DRAM row address strobe (TP4). |
| 5 | /CAS | ctrl | DRAM column address strobe (TP5). |
| 6 | E | clock | E clock to the 6809E pin 34, the PIAs and the cartridge (TP2). |
| 7 | Q | clock | Q clock to the 6809E pin 35 and the cartridge (TP3). |
| 8 | R/W | ctrl | Read/write from the CPU. |
| 9 | /RESET | ctrl | System reset. |
| 10 | /WE0 | ctrl | DRAM write enable, bank 0. |
| 11 | /WE1 | ctrl | DRAM write enable, bank 1. |
| 12 | CPUD0 | data | CPU data bus bit 0. |
| 13 | CPUD1 | data | CPU data bus bit 1. |
| 14 | CPUD2 | data | CPU data bus bit 2. |
| 15 | CPUD3 | data | CPU data bus bit 3. |
| 16 | CPUD4 | data | CPU data bus bit 4. |
| 17 | CPUD5 | data | CPU data bus bit 5. |
| 18 | CPUD6 | data | CPU data bus bit 6. |
| 19 | CPUD7 | data | CPU data bus bit 7. |
| 20 | /FIRQ | ctrl | Fast interrupt to the 6809E pin 4, from the GIME interrupt logic. UNVERIFIED |
| 21 | /IRQ | ctrl | Interrupt to the 6809E pin 3. |
| 22 | /IL0 | ctrl | Interrupt input 0 to the GIME interrupt logic. |
| 23 | /IL1 | ctrl | Interrupt input 1. |
| 24 | /IL2 | ctrl | Interrupt input 2. |
| 25 | A0 | addr | CPU address bit 0. |
| 26 | A1 | addr | CPU address bit 1. |
| 27 | A2 | addr | CPU address bit 2. |
| 28 | A3 | addr | CPU address bit 3. |
| 29 | S2 | ctrl | Device select bit 2, to the 74LS138 IC9. |
| 30 | S1 | ctrl | Device select bit 1. |
| 31 | S0 | ctrl | Device select bit 0. |
| 32 | Z0 | addr | Multiplexed DRAM address bit 0. |
| 33 | Z1 | addr | Multiplexed DRAM address bit 1. |
| 34 | Z2 | addr | Multiplexed DRAM address bit 2. |
| 35 | VDD | power | +5 V supply. |
| 36 | Z3 | addr | Multiplexed DRAM address bit 3. |
| 37 | Z4 | addr | Multiplexed DRAM address bit 4. |
| 38 | Z5 | addr | Multiplexed DRAM address bit 5. |
| 39 | TEST | ctrl | Factory test input. Tied off on the board. |
| 40 | Z6 | addr | Multiplexed DRAM address bit 6. |
| 41 | Z7 | addr | Multiplexed DRAM address bit 7. |
| 42 | Z8 | addr | Multiplexed DRAM address bit 8 (512K card). |
| 43 | A4 | addr | CPU address bit 4. |
| 44 | A5 | addr | CPU address bit 5. |
| 45 | A6 | addr | CPU address bit 6. |
| 46 | A7 | addr | CPU address bit 7. |
| 47 | A8 | addr | CPU address bit 8. |
| 48 | A9 | addr | CPU address bit 9. |
| 49 | A10 | addr | CPU address bit 10. |
| 50 | A11 | addr | CPU address bit 11. |
| 51 | A12 | addr | CPU address bit 12. |
| 52 | A13 | addr | CPU address bit 13. |
| 53 | A14 | addr | CPU address bit 14. |
| 54 | A15 | addr | CPU address bit 15. |
| 55 | VSYNC | video | Vertical sync, to RGB pin 9 and (through an inverter) PIA IC5 pin 18. |
| 56 | HSYNC | video | Horizontal sync, to RGB pin 8 and (through an inverter) PIA IC5 pin 40. |
| 57 | RAMD7 | data | DRAM data bus bit 7, into the GIME data latches (the service manual block diagram draws it as an input). |
| 58 | RAMD6 | data | DRAM data bus bit 6, into the GIME data latches (the service manual block diagram draws it as an input). |
| 59 | RAMD5 | data | DRAM data bus bit 5, into the GIME data latches (the service manual block diagram draws it as an input). |
| 60 | RAMD4 | data | DRAM data bus bit 4, into the GIME data latches (the service manual block diagram draws it as an input). |
| 61 | RAMD3 | data | DRAM data bus bit 3, into the GIME data latches (the service manual block diagram draws it as an input). |
| 62 | RAMD2 | data | DRAM data bus bit 2, into the GIME data latches (the service manual block diagram draws it as an input). |
| 63 | RAMD1 | data | DRAM data bus bit 1, into the GIME data latches (the service manual block diagram draws it as an input). |
| 64 | RAMD0 | data | DRAM data bus bit 0, into the GIME data latches (the service manual block diagram draws it as an input). |
| 65 | CVIDEO | video | Composite video, to the video jack and the modulator. |
| 66 | B | video | Blue analog output, to RGB pin 5 through an emitter follower. |
| 67 | G | video | Green analog output, to RGB pin 4 through an emitter follower. |
| 68 | R | video | Red analog output, to RGB pin 3 through an emitter follower. |
Fitted in
- Color Computer 3 IC6