Amstrad 40010 Gate Array (HSG3130 / HSG3170) pinout

DIP-40. Video (pixels, palette, RGB, sync), DRAM timing, ROM/RAM selection, CPU clock and wait states, interrupts

The same functions as the 40007 on a new pinout, cool enough to run without the plate. 16 MHz in on CK16 (pin 24); /PHI (pin 19) is inverted by a 74HCU04 to give the Z80 its 4 MHz; CCLK (pin 4) is the 1 MHz CRTC clock and /CPU (pin 14) the 1 MHz phase that also clocks the AY. On the 6128 the 40030 PAL beside it does the 128K banking. The late cost-down 6128 replaces Gate Array, CRTC and PAL with the 100-pin 40226.

Open the interactive 40010 pinout

Pins

Pin	Name	Type	Signal
1	D5	data	Data bus bit 5 (write-only chip).
2	D6	data	Data bit 6.
3	D7	data	Data bit 7.
4	CCLK	clock	Character clock to 6845 pin 21.
5	/SYNC	video	Composite sync to monitor DIN pin 4 through 220 ohms.
6	VDD1	power	+5 V.
7	/RESET	ctrl	System reset (expansion pin 41 through 82 ohms).
8	B	video	Blue drive to the RGB resistor network.
9	DISPEN	video	Display enable from 6845 pin 18.
10	G	video	Green drive.
11	HSYNC	video	Horizontal sync from 6845 pin 39.
12	R	video	Red drive.
13	VSYNC	video	Vertical sync from 6845 pin 40 (also 8255 PB0).
14	/CPU	clock	CPU/video phase: selects CPU address on the 74LS153 multiplexers; the same 1 MHz clocks the AY-3-8912.
15	VSS1	ground	0 V.
16	/CAS	ctrl	DRAM column address strobe (through the PAL on the 6128).
17	/MREQ	ctrl	Z80 memory request.
18	/IORQ	ctrl	Z80 I/O request.
19	/PHI	clock	Inverted CPU clock; a 74HCU04 makes the Z80 4 MHz from it.
20	/M1	ctrl	Z80 M1, interrupt acknowledge.
21	/RD	ctrl	Z80 read.
22	READY	ctrl	To Z80 /WAIT and expansion pin 39 (82 ohms).
23	/244EN	ctrl	Enables the 74LS244 data buffer IC115.
24	CK16	clock	16 MHz master clock from the 74HCU04 crystal oscillator (X101).
25	VDD2	power	+5 V.
26	VSS2	ground	0 V.
27	/ROMEN	ctrl	ROM enable: ROM /CS and expansion pin 42.
28	A15	addr	Address bit 15.
29	/RAMRD	ctrl	RAM read; ORed with RAMDIS to expansion pin 44 and the 74LS373 latch.
30	A14	addr	Address bit 14.
31	/CASAD	ctrl	Switches the address multiplexers from row to column address.
32	/INTERRUPT	ctrl	To Z80 /INT through 4.7K (expansion pin 35).
33	/MWE	ctrl	DRAM write enable.
34	/RAS	ctrl	DRAM row address strobe.
35	D0	data	Data bit 0.
36	VSS3	ground	0 V.
37	D1	data	Data bit 1.
38	D2	data	Data bit 2.
39	D3	data	Data bit 3.
40	D4	data	Data bit 4.

Fitted in

Amstrad CPC 464 IC116 on later boards (AMS40010, per the amendment)
Amstrad CPC 664 IC116 (HSG3130/3170)
Amstrad CPC 6128 IC116 (HSG3130/3170; socket J105)

Amstrad 40010 Gate Array (HSG3130 / HSG3170) pinout

Pins

Fitted in

Sources