Amstrad 40007 / 40008 Gate Array (20RA043) pinout

DIP-40. Video (pixels, palette, RGB, sync), DRAM timing, ROM/RAM selection, CPU clock and wait states, interrupts

The early CPC 464 Gate Array, fitted with a metal cooling plate. It divides the 16 MHz from a 7400 oscillator to 4 MHz for the Z80 (pin 39) and 1 MHz for the CRTC (pin 40), turns CRTC timing and RAM bytes into three-level RGB, and generates /RAS, /CAS and the address mux selects, READY (Z80 wait) and the 300 Hz interrupt. Write-only: the CPU programs it at I/O &7Fxx. The later 40010 does the same job on a different pinout; some boards take either. Missing heat plate or a dried pad gives faults that come with warm-up.

Open the interactive 40007 pinout

Pins

Pin	Name	Type	Signal
1	/CPU ADDR	ctrl	Selects CPU address (LOW) or CRTC address on the 74LS153 DRAM address multiplexers.
2	READY	ctrl	To Z80 /WAIT and expansion pin 39. Open collector with a 600 ohm pull-up.
3	/CAS	ctrl	DRAM column address strobe.
4	/244EN	ctrl	Enables the 74LS244 data buffer between CPU and RAM.
5	/MWE	ctrl	DRAM write enable.
6	/CAS ADDR	ctrl	Switches the address multiplexers from row to column address.
7	/RAS	ctrl	DRAM row address strobe.
8	XTAL	clock	16 MHz master clock from the 7400 crystal oscillator (X101).
9	VCC2	power	+5 V through resistor R138 (12 ohm).
10	/INTERRUPT	ctrl	To Z80 /INT. Open collector with a 5K pull-up.
11	/SYNC	video	Composite sync to monitor DIN pin 4.
12	/ROMEN	ctrl	ROM enable: to the ROM /CS and expansion pin 42.
13	/RAMRD	ctrl	RAM read; ORed with RAMDIS and sent to expansion pin 44.
14	HSYNC	video	Horizontal sync from the 6845.
15	VSYNC	video	Vertical sync from the 6845 (also to 8255 PB0).
16	/IORQ	ctrl	Z80 I/O request.
17	/M1	ctrl	Z80 M1, used to acknowledge the interrupt.
18	/MREQ	ctrl	Z80 memory request.
19	/RD	ctrl	Z80 read.
20	A15	addr	Address bit 15 (ROM and register decode).
21	A14	addr	Address bit 14.
22	VCC1	power	+5 V direct. Decouple close (C104).
23	DISPEN	video	Display enable from the 6845; border outside it.
24	D0	data	Data bus bit 0 (the Gate Array is written, never read).
25	D1	data	Data bit 1.
26	D2	data	Data bit 2.
27	D3	data	Data bit 3.
28	D4	data	Data bit 4.
29	D5	data	Data bit 5.
30	D6	data	Data bit 6.
31	D7	data	Data bit 7.
32	B	video	Blue drive to the RGB resistor network.
33	VCC2	power	+5 V through R138, as pin 9.
34	G	video	Green drive.
35	GND	ground	0 V. Decouple close.
36	R	video	Red drive.
37	/RESET	ctrl	System reset.
38	VCC1	power	+5 V direct.
39	PHI	clock	Z80 clock with a passive pull-up (to Z80 pin 6).
40	MA0/CCLK	clock	Character clock to the 6845 CLK input (schematic misprints NAD/CCLK).

Fitted in

Amstrad CPC 464 IC116 (20RA043 = Amstrad 40007; 40008 is pin compatible)

Amstrad 40007 / 40008 Gate Array (20RA043) pinout

Pins

Fitted in

Sources