251828 (64H156) 40/42-pin gate array pinout

DIP-40. Read/write, byte-ready, sync, stepper phases, serial ATN acknowledge and CPU clock select (1541B/C, 1541-II, 1571)

The second-generation drive gate array. 251828-01 is 40 pins (shown here); 251828-02 is 42 pins with the same pins 1-20, two extra pins 21-22, and pins 21-40 renumbered 23-42 (so OSC is 23, Vcc 32, BYTE 42). The 1571 service manual draws 21 as VCC and 22 as GND on the 42-pin part but its table calls them N/C; schematic 355207 shows 21 to +5 V and 22 to ground. ACCL selects a 1 MHz (1541) or 2 MHz (1571) CPU clock on CK. Ray Carlsen has never seen a bad one.

Open the interactive 251828 pinout

Pins

Pin	Name	Type	Signal
1	TEST	ctrl	Test input used in design verification.
2	YB0	data	Read/write data bit 0, to the disk VIA port A.
3	YB1	data	Read/write data bit 1.
4	YB2	data	Read/write data bit 2.
5	YB3	data	Read/write data bit 3.
6	YB4	data	Read/write data bit 4.
7	YB5	data	Read/write data bit 5.
8	YB6	data	Read/write data bit 6.
9	YB7	data	Read/write data bit 7.
10	VSS	ground	Ground.
11	STP1	ctrl	Stepper count bit, from the disk VIA port B. UNVERIFIED
12	STP0	ctrl	Stepper count bit, from the disk VIA port B. UNVERIFIED
13	MTR	ctrl	Motor control from the disk VIA PB2 (the manual says it activates the motor).
14	A	ctrl	Write protect input: disk is write protected.
15	DS0	ctrl	Density select bit 0: sets the bit-clock divide ratio for the zone.
16	DS1	ctrl	Density select bit 1.
17	SYNC	ctrl	Sync output to the disk VIA PB7 (LOW while a sync mark is read).
18	TED	ctrl	LOW clears BYTE in 2 MHz mode; HIGH sets 1541 mode.
19	OE	ctrl	Read/write mode: 0 write, 1 read. From the disk VIA CB2.
20	ACCL	ctrl	CPU clock select: 0 = 1 MHz (1541), 1 = 2 MHz (1571).
21	OSC	clock	16 MHz clock in.
22	ATNA	serial	Attention acknowledge from the serial VIA PB4.
23	ATNI	serial	ATN line in from the serial bus.
24	ATN	serial	ATN output: gates the serial DATA line through U16 (1571 block diagram and schematic 310420). The function table on p. 8 calls it an input. UNVERIFIED
25	Y0	ctrl	Stepper phase 0 output.
26	Y1	ctrl	Stepper phase 1 output.
27	Y2	ctrl	Stepper phase 2 output.
28	Y3	ctrl	Stepper phase 3 output.
29	/XRW	ctrl	RAM write enable output.
30	VCC	power	+5 V supply.
31	CLR	ctrl	HIGH when the read data is a logic 1. On the 1571 it comes from the 251829 saddle canceller.
32	PLL	clock	Clock compensation from the 20-pin gate array.
33	LOCK	ctrl	PLL lock: 1 = locked, 0 = internal sampling clock in use.
34	R/W	ctrl	CPU R/W select input.
35	Q	io	Write pulse output.
36	QX	io	Write pulse output (complement).
37	CK	clock	CPU clock out, 1 or 2 MHz.
38	B	ctrl	Write enable output.
39	SOE	ctrl	Enable byte (byte-ready enable) from the disk VIA CA2.
40	/BYTE	ctrl	Data latched (byte ready). To the disk VIA CA1 and the 6502 SO pin.

Fitted in

Commodore 1541 disk drive UC4 (1541B/1541C 250448), U10 (1541-II 340503)
Commodore 1571 disk drive U6

251828 (64H156) 40/42-pin gate array pinout

Pins

Fitted in

Sources