WD FD1771B-01 floppy disk formatter/controller pinout

DIP-40. Single-density disk controller in the Model I Expansion Interface, at $37EC-$37EF.

Single-density (FM) controller with an inverted data bus and three supplies: -5 V (pin 1), +5 V (pin 21) and +12 V (pin 40). In the Expansion Interface it runs from a 1 MHz clock (4 MHz crystal divided by 4) and the CPU polls it: DRQ (pin 38), TG43 and PH3 are not connected. Its registers sit at $37EC (command/status), $37ED (track), $37EE (sector) and $37EF (data). Lose -5 V or +12 V and it dies; check all three rails before swapping it.

Open the interactive 1771 pinout

Pins

PinNameTypeSignal
1VBBpower-5 V substrate supply.
2/WEctrlWrite enable. LOW gates the DAL into the selected register while /CS is LOW.
3/CSctrlChip select. LOW enables communication with the CPU.
4/REctrlRead enable. LOW puts the selected register on the DAL while /CS is LOW.
5A0addrRegister select bit 0. A1 A0: 00 status/command, 01 track, 10 sector, 11 data.
6A1addrRegister select bit 1.
7/DAL0dataData access line 0. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
8/DAL1dataData access line 1. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
9/DAL2dataData access line 2. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
10/DAL3dataData access line 3. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
11/DAL4dataData access line 4. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
12/DAL5dataData access line 5. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
13/DAL6dataData access line 6. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
14/DAL7dataData access line 7. Inverted bidirectional bus; buffered by Z33, Z37, Z38 in the EI.
15PH1/STEPctrlStep pulse (4 µs HIGH per step) when /3PM is HIGH; phase 1 of a three-phase motor otherwise.
16PH2/DIRCctrlDirection: HIGH steps in, LOW steps out (step/direction mode); phase 2 otherwise.
17PH3ctrlPhase 3 of a three-phase motor. Not connected in the EI.
18/3PMctrlThree-phase motor select. LOW selects three-phase outputs; HIGH selects step and direction (as wired in the EI).
19/MRctrlMaster reset. LOW resets the chip and loads 03H into the command register; a restore runs when it goes HIGH.
20VSSgroundGround.
21VCCpower+5 V.
22/TESTctrlFactory test input. Tie to +5 V or leave open.
23HLTctrlHead load timing. Sampled 10 ms after head load; HIGH means the head is engaged.
24CLKclockClock. The data sheet calls for 2 MHz; the EI feeds 1 MHz from the divide-by-4 counter (Z27, Z28) for 5.25-inch drives.
25/XTDSctrlExternal data separation. LOW selects an external separator; HIGH or open uses the internal one.
26FDCLOCKclockExternally separated clock when /XTDS is LOW; tie HIGH otherwise.
27FDDATAdataRaw read data from the drive (internal separator), or separated data. From READ DATA* through an inverter in the EI.
28HLDctrlHead load output. Not connected in the EI.
29TG43ctrlTrack greater than 43 (tracks 44-76). Not connected in the EI.
30WGctrlWrite gate. HIGH while writing. To WRITE GATE* (J5 pin 24) through a 7438 driver.
31WDdataWrite data: clock and data pulses of 500 ns. To WRITE DATA* (J5 pin 22).
32READYctrlDrive ready. Sampled HIGH before reads and writes; appears inverted as status bit 7.
33/WFctrlWrite fault from the drive. LOW while WG is HIGH ends the write command.
34/TR00ctrlTrack 00. LOW when the head is over track 0. From J5 pin 26.
35/IPctrlIndex pulse, LOW for at least 10 µs at the index hole. From J5 pin 8.
36/WPRTctrlWrite protect. LOW ends a write and sets the write-protect status bit. From J5 pin 28.
37/DINTctrlDisk initialization. Sampled on Write Track; LOW ends the command and sets write-protect status.
38DRQctrlData request, open drain (10 kΩ pull-up). Not connected in the EI.
39INTRQctrlInterrupt request, open drain. Set at the end of a command; reset by reading status. Feeds the EI interrupt latch read at $37E0.
40VDDpower+12 V.

Fitted in

Sources