Signetics 2661 EPCI (serial) pinout

DIP-28. The two HERO 2000 serial channels (serial A at $E8, serial B at $EC).

An enhanced programmable communications interface with its own baud-rate generator clocked on BRCLK. The HERO 2000 has two, decoded by the I/O PAL as 2661A ($E8-$EB, interrupt VI4) and 2661B ($EC-$EF, VI5); they drive the two 25-pin RS-232 connectors P410 and P412 (terminal and printer). /DCD and /CTS must be low or the receiver and transmitter stay off.

Open the interactive 2661 pinout

Pins

PinNameTypeSignal
1D2dataData bus bit 2.
2D3dataData bus bit 3.
3RxDserialSerial receive data (mark = high).
4GNDgroundGround.
5D4dataData bus bit 4.
6D5dataData bus bit 5.
7D6dataData bus bit 6.
8D7dataData bus bit 7 (MSB).
9/TxC /XSYNCclockTransmit clock in (1x, 16x, 64x), or with the internal clock a 1x/16x clock out or external sync input.
10A1addrRegister select bit 1.
11/CEctrlChip enable, active low; high floats D0-D7.
12A0addrRegister select bit 0.
13R/WctrlRead when low, write when high (the reverse of the 6800 sense).
14/RxRDYctrlReceiver ready, open drain; low when a character is waiting.
15/TxRDYctrlTransmitter ready, open drain; low when the holding register can take a character.
16/DCDserialData carrier detect; must be low for the receiver to run.
17/CTSserialClear to send; must be low for the transmitter to run.
18/TxEMT /DSCHGctrlTransmitter empty, or DSR/DCD change; open drain.
19TxDserialSerial transmit data; held at mark when disabled.
20BRCLKclockBaud-rate generator clock (4.9152 or 5.0688 MHz depending on version).
21RESETctrlMaster reset, active high.
22/DSRserialData set ready, general-purpose input.
23/RTSserialRequest to send, general-purpose output.
24/DTRserialData terminal ready, general-purpose output.
25/RxC /BKDETclockReceive clock in, or with the internal clock a 1x/16x clock out or break-detect output.
26VCCpower+5 V supply.
27D0dataData bus bit 0 (LSB).
28D1dataData bus bit 1.

Fitted in

Sources