Electron ULA (Ferranti 12C021) pinout

PLCC-68. Video, 4-bit DRAM control, CPU clock (2 / 1 MHz / stopped), ROM select and paging, keyboard read, cassette, sound, interrupts: every register at &FE00-&FE0F UNVERIFIED

One 68-pin Ferranti ULA does nearly everything on the Electron: it divides the 16 MHz clock, feeds the 6502 its PHI clock (2 MHz for ROM, 1 MHz for RAM and I/O, stopped while the screen owns RAM in MODEs 0-3), runs the four 4164s as a 4-bit RAM (two accesses per byte), makes RGB and sync, the cassette and sound, scans the keyboard and raises IRQ. The service manual calls it a 68-pin quad in-line package: a square carrier with 17 contacts a side, pin 1 marked at the top left and the pins running anti-clockwise. It is drawn here with pin 1 at the top-left corner, numbered anti-clockwise as the manual states; the manual does not say which edge the numbering starts along, so the orientation of the drawing is unverified. On issue 2 and 4 boards it sits in a clip-down socket that is the machine's weak point: reseat and clean it before condemning the chip. Issue 6 boards solder it in. A good spare ULA is the service manual's first test.

Open the interactive ULA pinout

Pins

Pin	Name	Type	Signal
1	A1	addr	6502 address bit 1 in.
2	A8	addr	6502 address bit 8 in.
3	RED	video	Red, TTL active high, to RGB pin 1 (R47) and the PAL encoder.
4	GREEN	video	Green, to RGB pin 2 (R46) and the encoder.
5	A0	addr	6502 address bit 0 in.
6	RA7	addr	Multiplexed DRAM address 7 to the 4164 A7 (row, then column).
7	RA6	addr	Multiplexed DRAM address 6 to the 4164 A6 (row, then column).
8	RA5	addr	Multiplexed DRAM address 5 to the 4164 A5 (row, then column).
9	VCC2	power	+5 V through R5 24R 1/2 W (so a little under the rail).
10	A14	addr	6502 address bit 14 in.
11	RA4	addr	Multiplexed DRAM address 4 to the 4164 A4 (row, then column).
12	A2	addr	6502 address bit 2 in.
13	A12	addr	6502 address bit 12 in.
14	A13	addr	6502 address bit 13 in.
15	A7	addr	6502 address bit 7 in.
16	RA3	addr	Multiplexed DRAM address 3 to the 4164 A3 (row, then column).
17	A6	addr	6502 address bit 6 in.
18	RA2	addr	Multiplexed DRAM address 2 to the 4164 A2 (row, then column).
19	RA1	addr	Multiplexed DRAM address 1 to the 4164 A1 (row, then column).
20	A5	addr	6502 address bit 5 in.
21	A4	addr	6502 address bit 4 in.
22	RA0	addr	Multiplexed DRAM address 0 to the 4164 A0 (row, then column).
23	A11	addr	6502 address bit 11 in.
24	A3	addr	6502 address bit 3 in.
25	A10	addr	6502 address bit 10 in.
26	A9	addr	6502 address bit 9 in.
27	KBD0	kbd	Keyboard return line 0 from PL2 pin 5.
28	KBD1	kbd	Keyboard return line 1 from PL2 pin 6.
29	/WE	ctrl	DRAM write enable to the 4164 pin 3: low = write, high = read.
30	/IRQ	ctrl	Interrupt request to the 6502 pin 4 and expansion pin 17. Open collector, 3k3 pull-up inside the ULA.
31	KBD2	kbd	Keyboard return line 2 from PL2 pin 7.
32	KBD3	kbd	Keyboard return line 3 from PL2 pin 8.
33	PD0	data	6502 data bus bit 0.
34	RAM0	data	RAM data line 0, to DIN and DOUT of IC4 (bits 0 and 1 of each byte, in two accesses).
35	PD1	data	6502 data bus bit 1.
36	PD2	data	6502 data bus bit 2.
37	RAM1	data	RAM data line 1, to IC5 (bits 2 and 3).
38	PD3	data	6502 data bus bit 3.
39	PD4	data	6502 data bus bit 4.
40	RAM2	data	RAM data line 2, to IC6 (bits 4 and 5).
41	PD5	data	6502 data bus bit 5.
42	PD6	data	6502 data bus bit 6.
43	VCC2	power	+5 V through R58 24R 1/2 W.
44	RAM3	data	RAM data line 3, to IC7 (bits 6 and 7).
45	PD7	data	6502 data bus bit 7.
46	R/W	ctrl	Read/not write from the 6502 pin 34: 1 = read, 0 = write.
47	CAS RC	audio	To an RC network (R6 56K, C8 1 uF, D5) that detects a continuous high tone on tape.
48	VCC1	power	+5 V direct.
49	CLOCK IN	clock	16 MHz from the 74S04 oscillator IC8 pin 8.
50	CAS OUT	audio	Pseudo-sine cassette output to the LM324 buffer.
51	GND	ground	0 V.
52	/RAS	ctrl	Row address strobe to the 4164 pin 4; also does refresh.
53	/CAS	ctrl	Column address strobe to the 4164 pin 15.
54	/POR	ctrl	Power-on reset: R7 56K and C9 1 uF give a rising edge at switch-on that resets the ULA, which then pulls /RST.
55	÷13 IN	clock	16 MHz divided by 13 from the 74LS169 IC9 pin 11: the cassette and baud timing.
56	A15	addr	6502 address bit 15 in.
57	/NMI	ctrl	System NMI (6502 pin 6, expansion pin 16), 3k3 pull-up inside the ULA. While NMI is active the CPU gets full 1 MHz RAM access in any mode.
58	/RST	ctrl	Reset to the 6502 pin 40 and expansion pin 15: low at power-up and while BREAK is held.
59	CAS IN	audio	Cassette input from the LM324 amplifier (IC13 pin 14) through C7.
60	PHI OUT	clock	The 6502 clock (6502 pin 37, expansion pin 14), made from 16 MHz: 2 MHz for ROM, 1 MHz for RAM and I/O, stopped while the screen uses RAM in MODEs 0-3.
61	ROM	ctrl	ROM select for the OS/BASIC ROM IC2 (enables reads from it).
62	SOUND O/P	audio	Tone from the internal sound counter to the Q3/Q4 speaker driver and, through 1K, expansion pin 11.
63	CAPS LOCK	io	CAPS LOCK LED drive, PL2 pin 2.
64	CAS MO	ctrl	Tape motor: drives Q6 and relay RL1.
65	/CSYNC	video	Composite sync, low during H or V sync, to 74LS86 IC14 pin 13 and the encoder.
66	BLUE	video	Blue, to RGB pin 3 (R45) and the encoder.
67	/HS	video	Horizontal sync only (low during line sync), to the PAL chroma logic.
68	GND	ground	0 V.

Fitted in

Acorn Electron IC1 (Acorn 201,620)

Electron ULA (Ferranti 12C021) pinout

Pins

Fitted in

Sources