41256 DRAM 256K x 1 pinout
DIP-16. Dynamic RAM, 256K x 1
256K x 1 dynamic RAM on +5 V only. Nine multiplexed address bits: pin 1 is A8, which is NC on a 4164; every other pin matches the 4164. It needs all 256 rows (A0 to A7) refreshed every 4 ms. On the IBM 5160 256-640KB board banks 0 and 1 are 41256 and banks 2 and 3 are 4164, all 200 ns or faster.
Open the interactive 41256 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | A8 | addr | Multiplexed address bit 8. NC on a 4164, so a 41256 in a 4164 board needs this pin driven or tied. |
| 2 | DIN | data | Data in. |
| 3 | /WE | ctrl | Write enable. LOW writes DIN. |
| 4 | /RAS | ctrl | Row address strobe. Latches the row address; a RAS-only cycle refreshes the row. |
| 5 | A0 | addr | Multiplexed address bit 0. |
| 6 | A2 | addr | Multiplexed address bit 2. |
| 7 | A1 | addr | Multiplexed address bit 1. |
| 8 | VCC | power | +5 V, the only supply. |
| 9 | A7 | addr | Multiplexed address bit 7. |
| 10 | A5 | addr | Multiplexed address bit 5. |
| 11 | A4 | addr | Multiplexed address bit 4. |
| 12 | A3 | addr | Multiplexed address bit 3. |
| 13 | A6 | addr | Multiplexed address bit 6. |
| 14 | DOUT | data | Data out, three-state; driven only while /CAS is LOW on a read. |
| 15 | /CAS | ctrl | Column address strobe. Latches the column address and gates DOUT. |
| 16 | VSS | ground | 0 V. |
Fitted in
- IBM XT 5160 Banks 0 and 1 on the 256-640KB board (banks 2 and 3 are 4164)
- IBM Portable 5155 Banks 0 and 1 on the photographed board: HY53C256LS-10 (CMOS 256K x 1), a later upgrade; the 64-256KB board takes 4164s in all four banks
Sources
- Hitachi HM50256 data sheet, features and pin arrangement, 1984 IC Memory Data Book p. 219
- TI TMS4256 data sheet (pinout, 256-row 4 ms refresh, upward pin compatible with TMS4164), 1984 MOS Memory Data Book p. 4-63
- minuszerodegrees.net, IBM 5160 RAM on a 256-640KB motherboard
- Same page, Wayback Machine copy (Mar 2026; the site refuses some clients with HTTP 406)