8237A-5 DMA controller pinout
DIP-40. Four DMA channels. PC: channel 0 refreshes DRAM, channel 2 is the diskette.
Four DMA channels at ports $00 to $0F; the -5 part runs to 5 MHz. On the 5150 (U35) channel 0 does DRAM refresh, paced by timer 1, and channel 2 serves the diskette adapter. It puts address bits A8 to A15 out on its data pins, latched by ADSTB; a page register at $80 to $83 adds A16 to A19. A dead DMA gives lost memory and no diskette transfers.
Open the interactive 8237A pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | /IOR | ctrl | I/O read, active LOW, three-state. Input when the CPU reads the 8237A; output during a DMA write (peripheral to memory). |
| 2 | /IOW | ctrl | I/O write, active LOW, three-state. Input when the CPU programs it; output during a DMA read (memory to peripheral). |
| 3 | /MEMR | ctrl | Memory read, active LOW, three-state. |
| 4 | /MEMW | ctrl | Memory write, active LOW, three-state. |
| 5 | PIN 5 | power | Must be held HIGH. Has an internal pull-up and may be tied to VCC. 5150: tied to +5 V. |
| 6 | READY | ctrl | Ready, active HIGH. LOW stretches the memory strobes for slow parts. |
| 7 | HLDA | ctrl | Hold acknowledge, active HIGH: the bus is free. |
| 8 | ADSTB | ctrl | Address strobe, active HIGH. Latches A8 to A15 from DB0 to DB7 into an external latch. |
| 9 | AEN | ctrl | Address enable, active HIGH. Enables the upper-address latch and can turn off other bus drivers. 5150: not connected (the board makes AEN in its own logic). |
| 10 | HRQ | ctrl | Hold request, active HIGH. Any unmasked DREQ raises it. |
| 11 | /CS | ctrl | Chip select, active LOW. PC: ports $00 to $0F. |
| 12 | CLK | clock | Clock input, up to 5 MHz for the -5 part. |
| 13 | RESET | ctrl | Reset, active HIGH. Clears the Command, Status, Request and Temporary registers and the first/last flip-flop, and sets the Mask register. Address, count and base registers are not cleared. |
| 14 | DACK2 | ctrl | DMA acknowledge 2. Sense set by software; reset makes it active LOW. PC: diskette (I/O channel B26). |
| 15 | DACK3 | ctrl | DMA acknowledge 3. PC: I/O channel B15. |
| 16 | DREQ3 | ctrl | DMA request 3. Polarity set by software; reset makes it active HIGH. PC: I/O channel B16. |
| 17 | DREQ2 | ctrl | DMA request 2. PC: diskette adapter DRQ2 (I/O channel B6). |
| 18 | DREQ1 | ctrl | DMA request 1. PC: I/O channel B18. |
| 19 | DREQ0 | ctrl | DMA request 0, highest fixed priority. PC: refresh request from timer 1. |
| 20 | GND | ground | Ground (VSS). |
| 21 | DB7 | data | Data bus bit 7. Carries address bit A15 early in a DMA cycle, latched by ADSTB. |
| 22 | DB6 | data | Data bus bit 6 (A14 during DMA). |
| 23 | DB5 | data | Data bus bit 5 (A13 during DMA). |
| 24 | DACK1 | ctrl | DMA acknowledge 1. PC: I/O channel B17. |
| 25 | DACK0 | ctrl | DMA acknowledge 0. PC: refresh cycle (I/O channel B19). |
| 26 | DB4 | data | Data bus bit 4 (A12 during DMA). |
| 27 | DB3 | data | Data bus bit 3 (A11 during DMA). |
| 28 | DB2 | data | Data bus bit 2 (A10 during DMA). |
| 29 | DB1 | data | Data bus bit 1 (A9 during DMA). |
| 30 | DB0 | data | Data bus bit 0 (A8 during DMA). |
| 31 | VCC | power | +5 V supply. |
| 32 | A0 | addr | Address bit 0. Input when the CPU selects a register; output during DMA. |
| 33 | A1 | addr | Address bit 1. |
| 34 | A2 | addr | Address bit 2. |
| 35 | A3 | addr | Address bit 3. |
| 36 | /EOP | ctrl | End of process, active LOW. Pulses at terminal count; pulling it LOW ends a transfer. PC: inverted to T/C on I/O channel B27. |
| 37 | A4 | addr | Address bit 4, three-state, driven only during DMA. |
| 38 | A5 | addr | Address bit 5. |
| 39 | A6 | addr | Address bit 6. |
| 40 | A7 | addr | Address bit 7. |