6545 CRTC pinout
DIP-40. Video timing and screen addressing (later PET boards)
CRT controller that makes the sync, display-enable and cursor and gives the screen RAM addresses. Only on later PET and 80-column boards. Early 2001s used discrete logic and have no CRTC, so a missing CRTC there is normal. Fails as no, rolling or distorted display.
Open the interactive CRTC pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | Vss | ground | 0 V. |
| 2 | /RES | ctrl | Reset. LOW resets the CRTC. |
| 3 | LPEN | ctrl | Light pen input. |
| 4 | MA0 | addr | Memory address bit 0 to the screen RAM. |
| 5 | MA1 | addr | Memory address bit 1 to the screen RAM. |
| 6 | MA2 | addr | Memory address bit 2 to the screen RAM. |
| 7 | MA3 | addr | Memory address bit 3 to the screen RAM. |
| 8 | MA4 | addr | Memory address bit 4 to the screen RAM. |
| 9 | MA5 | addr | Memory address bit 5 to the screen RAM. |
| 10 | MA6 | addr | Memory address bit 6 to the screen RAM. |
| 11 | MA7 | addr | Memory address bit 7 to the screen RAM. |
| 12 | MA8 | addr | Memory address bit 8 to the screen RAM. |
| 13 | MA9 | addr | Memory address bit 9 to the screen RAM. |
| 14 | MA10 | addr | Memory address bit 10 to the screen RAM. |
| 15 | MA11 | addr | Memory address bit 11 to the screen RAM. |
| 16 | MA12 | addr | Memory address bit 12 to the screen RAM. |
| 17 | MA13 | addr | Memory address bit 13 to the screen RAM. |
| 18 | DE | ctrl | Display enable: HIGH while the picture is being drawn. |
| 19 | CURSOR | ctrl | Cursor output. |
| 20 | Vcc | power | +5 V supply. |
| 21 | CCLK | clock | Character clock input from the video timing. |
| 22 | R/W | ctrl | Read/write from the CPU. |
| 23 | Φ2 (E) | clock | Phase 2 (E) clock from the CPU. |
| 24 | RS | ctrl | Register select: picks address or data register. |
| 25 | /CS | ctrl | Chip select, LOW to access the CRTC registers. |
| 26 | D7 | data | Data bus bit 7. |
| 27 | D6 | data | Data bus bit 6. |
| 28 | D5 | data | Data bus bit 5. |
| 29 | D4 | data | Data bus bit 4. |
| 30 | D3 | data | Data bus bit 3. |
| 31 | D2 | data | Data bus bit 2. |
| 32 | D1 | data | Data bus bit 1. |
| 33 | D0 | data | Data bus bit 0. |
| 34 | RA4 | addr | Raster address bit 4 (character-row scan line to the character ROM). |
| 35 | RA3 | addr | Raster address bit 3. |
| 36 | RA2 | addr | Raster address bit 2. |
| 37 | RA1 | addr | Raster address bit 1. |
| 38 | RA0 | addr | Raster address bit 0. |
| 39 | HSYNC | video | Horizontal sync to the monitor. |
| 40 | VSYNC | video | Vertical sync to the monitor. |