8502 CPU pinout

DIP-40. CPU (6510 family, native C128 mode)

C128 main CPU at 1 or 2 MHz (FAST). 6510-family with a 7-bit I/O port (P0-P6, pins 30-24) for tape and serial. It has no φ2 output pin: R/W moves to pin 39 and the data bus to pins 38-31. Dead in every mode points here, the MMU or the PLA.

Open the interactive 8502 pinout

Pins

Pin	Name	Type	Signal
1	Φ0 in	clock	Clock input (Φ0).
2	RDY	ctrl	Ready. Pull LOW to stall the CPU.
3	/IRQ	ctrl	Interrupt request.
4	/NMI	ctrl	Non-maskable interrupt.
5	AEC	ctrl	Address Enable Control. LOW tri-states the address bus for the video chip.
6	+5V	power	+5 V supply.
7	A0	addr	Address bus bit 0.
8	A1	addr	Address bus bit 1.
9	A2	addr	Address bus bit 2.
10	A3	addr	Address bus bit 3.
11	A4	addr	Address bus bit 4.
12	A5	addr	Address bus bit 5.
13	A6	addr	Address bus bit 6.
14	A7	addr	Address bus bit 7.
15	A8	addr	Address bus bit 8.
16	A9	addr	Address bus bit 9.
17	A10	addr	Address bus bit 10.
18	A11	addr	Address bus bit 11.
19	A12	addr	Address bus bit 12.
20	A13	addr	Address bus bit 13.
21	GND	ground	0 V.
22	A14	addr	Address bus bit 14.
23	A15	addr	Address bus bit 15.
24	P6	io	Processor port bit 6: CAPS LOCK sense on the C128 (schematic: CAPLK SENSE). UNVERIFIED
25	P5	io	Processor port bit 5: Datasette motor (CASS MTR/P5).
26	P4	io	Processor port bit 4: Datasette sense (CASS SENSE/P4).
27	P3	io	Processor port bit 3: Datasette write (CASS WRT/P3).
28	P2	io	Processor port bit 2: CHAREN (C64-mode memory map).
29	P1	io	Processor port bit 1: HIRAM (C64-mode memory map).
30	P0	io	Processor port bit 0: LORAM (C64-mode memory map).
31	D7	data	Data bus bit 7.
32	D6	data	Data bus bit 6.
33	D5	data	Data bus bit 5.
34	D4	data	Data bus bit 4.
35	D3	data	Data bus bit 3.
36	D2	data	Data bus bit 2.
37	D1	data	Data bus bit 1.
38	D0	data	Data bus bit 0.
39	R/W	ctrl	Read/write from the CPU. HIGH = read. Moved to pin 39 on the 8502.
40	/RES	ctrl	Reset. LOW at power-up, released HIGH.

Fitted in

Commodore 128 U6

Sources

C128 Service Manual, 8502 pinout and pin description, p. 7