8088 microprocessor pinout
DIP-40. CPU with a 16-bit core and an 8-bit external bus. Used in the IBM 5150, 5160, 5155, PCjr and the HERO 2000.
A 16-bit core on an 8-bit external bus, so every 16-bit word takes two bus cycles. Pin 33 (MN/MX) sets the mode. Strapped LOW (maximum mode), an 8288 makes the bus strobes and pins 24 to 31 change function. Strapped HIGH (minimum mode), the CPU makes the strobes itself. The IBM 5150, 5160 and 5155 run it in maximum mode; the PCjr runs it in minimum mode. AD0 to AD7 carry the address and then the data, so an external latch holds the address on ALE.
Open the interactive 8088 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | GND | ground | Ground. Pins 1 and 20 are both ground. |
| 2 | A14 | addr | Address bit 14. Valid for the whole bus cycle (T1 to T4), so it needs no latch. Floats in hold acknowledge. Pins 2 to 8 are A14 to A8. |
| 3 | A13 | addr | Address bit 13. |
| 4 | A12 | addr | Address bit 12. |
| 5 | A11 | addr | Address bit 11. |
| 6 | A10 | addr | Address bit 10. |
| 7 | A9 | addr | Address bit 9. |
| 8 | A8 | addr | Address bit 8. |
| 9 | AD7 | data | Multiplexed address and data bit 7. Address in T1, data in T2 to T4. Floats in interrupt acknowledge and hold acknowledge. |
| 10 | AD6 | data | Multiplexed address and data bit 6. |
| 11 | AD5 | data | Multiplexed address and data bit 5. |
| 12 | AD4 | data | Multiplexed address and data bit 4. |
| 13 | AD3 | data | Multiplexed address and data bit 3. |
| 14 | AD2 | data | Multiplexed address and data bit 2. |
| 15 | AD1 | data | Multiplexed address and data bit 1. |
| 16 | AD0 | data | Multiplexed address and data bit 0. |
| 17 | NMI | ctrl | Non-maskable interrupt. A LOW-to-HIGH edge causes a type 2 interrupt at the end of the current instruction. Software cannot mask it. |
| 18 | INTR | ctrl | Maskable interrupt request, level-triggered, active HIGH. Sampled in the last clock of each instruction; masked by the interrupt-enable flag. |
| 19 | CLK | clock | Clock input, 33 percent duty cycle, normally from an 8284A CLK output. |
| 20 | GND | ground | Ground. |
| 21 | RESET | ctrl | Reset, active HIGH for at least four clocks. Execution restarts at $FFFF0 when it goes LOW. |
| 22 | READY | ctrl | Ready, active HIGH, from the addressed memory or I/O through the 8284A synchronizer. LOW adds wait states. Not synchronized inside the CPU. |
| 23 | /TEST | ctrl | Tested by the WAIT instruction. LOW lets execution continue; HIGH makes WAIT idle. An 8087 BUSY output drives it in a coprocessor system. |
| 24 | /INTA (QS1) | ctrl | Minimum mode: interrupt-acknowledge read strobe, active LOW. Maximum mode: queue status bit QS1, read by an 8087. |
| 25 | ALE (QS0) | ctrl | Minimum mode: address latch enable, a HIGH pulse in T1; the address latches on its falling edge. Never floats. Maximum mode: queue status bit QS0 (the 8288 makes ALE). |
| 26 | /DEN (/S0) | ctrl | Minimum mode: data enable for the bus transceivers, active LOW. Maximum mode: status /S0 to the 8288. |
| 27 | DT/R (/S1) | ctrl | Minimum mode: data transmit (HIGH) or receive (LOW) for the transceivers. Maximum mode: status /S1 to the 8288. |
| 28 | IO/M (/S2) | ctrl | Minimum mode: HIGH for an I/O cycle, LOW for memory. Maximum mode: status /S2 to the 8288. |
| 29 | /WR (/LOCK) | ctrl | Minimum mode: write strobe, active LOW in T2, T3 and Tw (it goes HIGH entering T4). Maximum mode: /LOCK, active LOW while a LOCK-prefixed instruction runs, to keep other bus masters off. |
| 30 | HLDA (/RQ/GT1) | ctrl | Minimum mode: hold acknowledge output, HIGH. Maximum mode: request/grant 1, active-LOW pulses, lower priority than pin 31. Has an internal pull-up. |
| 31 | HOLD (/RQ/GT0) | ctrl | Minimum mode: hold request input, HIGH. Maximum mode: request/grant 0, higher priority. Has an internal pull-up. |
| 32 | /RD | ctrl | Read strobe, active LOW in T2, T3 and Tw of a read (it goes HIGH entering T4). Present in both modes; floats in hold acknowledge. |
| 33 | MN/MX | ctrl | Mode strap. HIGH (VCC) is minimum mode: the CPU makes its own strobes. LOW (GND) is maximum mode: an 8288 makes them. |
| 34 | /SS0 | ctrl | Minimum mode: status line, the same as /S0 in maximum mode. With IO/M and DT/R it decodes the bus cycle. Maximum mode: always HIGH. |
| 35 | A19/S6 | addr | Address bit 19 in T1. Status S6 (always LOW) in T2 to T4. LOW during I/O cycles. |
| 36 | A18/S5 | addr | Address bit 18 in T1. Status S5 in T2 to T4 is the interrupt-enable flag. |
| 37 | A17/S4 | addr | Address bit 17 in T1. Status S4 in T2 to T4: with S3 it shows the segment register in use. |
| 38 | A16/S3 | addr | Address bit 16 in T1. Status S3 in T2 to T4: with S4 it shows the segment register in use. |
| 39 | A15 | addr | Address bit 15. Valid for the whole bus cycle. |
| 40 | VCC | power | +5 V supply, 10 percent. |