7501 / 8501 CPU pinout

DIP-40. CPU

HMOS 6510 variant running at 0.89 MHz (TED busy) / 1.79 MHz (dual-speed; NTSC figures, PAL 0.88 / 1.77 MHz). Has a 7-bit on-chip I/O port (P0-P4, P6, P7) that drives the Datasette and IEC serial bus. GATE IN holds R/W off until /RAS. The 8501 is identical. No /NMI pin.

Open the interactive 7501 pinout

Pins

Pin	Name	Type	Signal
1	Φ0 IN	clock	Clock input (PHI IN). Fed by TED pin 12 at 0.89 / 1.79 MHz (NTSC).
2	RDY	ctrl	Ready. HIGH lets the CPU run; TED pulls it LOW (via BA) to steal bus cycles.
3	/IRQ	ctrl	Interrupt request from TED (raster, timers) and the 6551 on the Plus/4.
4	AEC	ctrl	Address Enable Control. LOW tri-states the CPU address bus so TED can fetch.
5	VCC	power	+5 V supply.
6	A0	addr	Address bus bit 0.
7	A1	addr	Address bus bit 1.
8	A2	addr	Address bus bit 2.
9	A3	addr	Address bus bit 3.
10	A4	addr	Address bus bit 4.
11	A5	addr	Address bus bit 5.
12	A6	addr	Address bus bit 6.
13	A7	addr	Address bus bit 7.
14	A8	addr	Address bus bit 8.
15	A9	addr	Address bus bit 9.
16	A10	addr	Address bus bit 10.
17	A11	addr	Address bus bit 11.
18	A12	addr	Address bus bit 12.
19	A13	addr	Address bus bit 13.
20	GND	ground	0 V.
21	A14	addr	Address bus bit 14.
22	A15	addr	Address bus bit 15.
23	GATE	ctrl	GATE IN. Holds R/W off until /RAS goes from LOW to HIGH; the TED MUX output usually drives it.
24	P7	io	Port bit 7: serial DATA in (reads the IEC DATA line, schematic 251788). UNVERIFIED
25	P6	io	Port bit 6: serial CLK in (reads the IEC CLK line). UNVERIFIED
26	P4	io	Port bit 4: Datasette read (CST RD).
27	P3	io	Port bit 3: Datasette motor control (CST MTR, drives Q5).
28	P2	io	Port bit 2: serial ATN out (through a 7406 inverter).
29	P1	io	Port bit 1: serial CLK out (through a 7406) and Datasette write.
30	P0	io	Port bit 0: serial DATA out (through a 7406 inverter).
31	DB7	data	Data bus bit 7.
32	DB6	data	Data bus bit 6.
33	DB5	data	Data bus bit 5.
34	DB4	data	Data bus bit 4.
35	DB3	data	Data bus bit 3.
36	DB2	data	Data bus bit 2.
37	DB1	data	Data bus bit 1.
38	DB0	data	Data bus bit 0.
39	R/W	ctrl	Read (HIGH) / Write (LOW) level for the whole bus.
40	/RES	ctrl	Reset. Held LOW at power-up, then HIGH. Stuck LOW = dead machine.

Fitted in

Commodore 16 U2
Commodore Plus/4 U2

7501 / 8501 CPU pinout

Pins

Fitted in

Sources