MC6803 CPU (ROMless 6801) pinout
DIP-40. MC-10 main CPU. A ROMless 6801 with the address and data multiplexed on ports 3 and 4.
The 6803 runs the MC-10 in mode 2 at 0.89 MHz. Port 3 carries the multiplexed A0-A7/D0-D7 bus, port 4 carries A8-A15, port 1 scans the keyboard and port 2 handles RS-232, cassette and the mode pins. No boot is usually the 6803, its 3.58 MHz clock from the modulator, or the ROM. Bad keys can be the keyboard matrix or port 1.
Open the interactive 6803 pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | Vss | ground | Ground. |
| 2 | XTAL1 | clock | Crystal pin 1 of the on-chip oscillator. |
| 3 | EXTAL2 | clock | Clock input. The MC-10 feeds 3.579545 MHz from the modulator unit here; the 6803 divides by 4. |
| 4 | /NMI | ctrl | Non-maskable interrupt. Active LOW. |
| 5 | /IRQ1 | ctrl | Maskable interrupt 1. Active LOW. |
| 6 | /RESET | ctrl | Reset, buffered by U12 because the input has no hysteresis. LOW for a few ms at power-up. |
| 7 | Vcc | power | +5 V supply. |
| 8 | P20 | io | Port 2 bit 0. Shared RS-232 and cassette output. LOW at reset (mode select). |
| 9 | P21 | io | Port 2 bit 1. Pulled HIGH at reset to select mode 2. |
| 10 | P22 | io | Port 2 bit 2. RS-232 data in. LOW at reset (mode select). |
| 11 | P23 | io | Port 2 bit 3. RS-232 CD in. |
| 12 | P24 | io | Port 2 bit 4. Cassette data in. |
| 13 | P10 | kbd | Port 1 bit 0. Keyboard line KR0. |
| 14 | P11 | kbd | Port 1 bit 1. Keyboard line KR1. |
| 15 | P12 | kbd | Port 1 bit 2. Keyboard line KR2. |
| 16 | P13 | kbd | Port 1 bit 3. Keyboard line KR3. |
| 17 | P14 | kbd | Port 1 bit 4. Keyboard line KR4. |
| 18 | P15 | kbd | Port 1 bit 5. Keyboard line KR5. |
| 19 | P16 | kbd | Port 1 bit 6. Keyboard line KR6. |
| 20 | P17 | kbd | Port 1 bit 7. Keyboard line KR7. |
| 21 | Vcc Stby | power | Standby supply for the on-chip RAM. Tied to +5 V on the MC-10. |
| 22 | P47 | addr | Port 4 bit 7. Address A15 out. |
| 23 | P46 | addr | Port 4 bit 6. Address A14 out. |
| 24 | P45 | addr | Port 4 bit 5. Address A13 out. |
| 25 | P44 | addr | Port 4 bit 4. Address A12 out. |
| 26 | P43 | addr | Port 4 bit 3. Address A11 out. |
| 27 | P42 | addr | Port 4 bit 2. Address A10 out. |
| 28 | P41 | addr | Port 4 bit 1. Address A9 out. |
| 29 | P40 | addr | Port 4 bit 0. Address A8 out. |
| 30 | P37 | data | Port 3 bit 7. Multiplexed A7/D7; the 74LS373 U2 latches the address. UNVERIFIED |
| 31 | P36 | data | Port 3 bit 6. Multiplexed A6/D6; the 74LS373 U2 latches the address. |
| 32 | P35 | data | Port 3 bit 5. Multiplexed A5/D5; the 74LS373 U2 latches the address. |
| 33 | P34 | data | Port 3 bit 4. Multiplexed A4/D4; the 74LS373 U2 latches the address. |
| 34 | P33 | data | Port 3 bit 3. Multiplexed A3/D3; the 74LS373 U2 latches the address. |
| 35 | P32 | data | Port 3 bit 2. Multiplexed A2/D2; the 74LS373 U2 latches the address. |
| 36 | P31 | data | Port 3 bit 1. Multiplexed A1/D1; the 74LS373 U2 latches the address. |
| 37 | P30 | data | Port 3 bit 0. Multiplexed A0/D0; the 74LS373 U2 latches the address. |
| 38 | R/W | ctrl | Read/write. HIGH = read. |
| 39 | AS | ctrl | Address strobe. Latches A0-A7 into the 74LS373 U2. |
| 40 | E | clock | Enable clock out, 0.89 MHz (input clock / 4). The bus timing clock. |
Fitted in
- MC-10 U1