ANTIC CO12296 / C021697 display processor pinout
DIP-40. Display list processor: fetches screen data by DMA, halts the CPU, makes the NMI for VBlank and DLI, refreshes DRAM.
ANTIC reads the display list and fetches screen memory by DMA. It steals bus cycles by pulling HALT low, holds the CPU on RDY for WSYNC, and makes the NMI for vertical blank and display list interrupts. It takes the fast clock from GTIA and hands PHI0 to the CPU, so a dead ANTIC stops the whole machine, not only the picture. The 400/800 part is CO12296; the 600XL, 800XL and 130XE parts lists give C021697.
Open the interactive ANTIC pinoutPins
| Pin | Name | Type | Signal |
|---|---|---|---|
| 1 | Vss | ground | 0 V. |
| 2 | AN0 | video | Alphanumeric (playfield) data bit 0 to GTIA pin 18. |
| 3 | AN1 | video | Alphanumeric data bit 1 to GTIA pin 19. |
| 4 | /LP | ctrl | Light pen input. |
| 5 | AN2 | video | Alphanumeric data bit 2 to GTIA pin 20. |
| 6 | /RNMI | ctrl | Reset-key NMI input (the 800XL manual labels it SYS RST). 3 kΩ pull-up on the 130XE. |
| 7 | /NMI | ctrl | NMI to the CPU: vertical blank and display list interrupts. UNVERIFIED |
| 8 | /REF | ctrl | DRAM refresh strobe. |
| 9 | /HALT | ctrl | Halts the CPU while ANTIC fetches screen data. Also goes to GTIA pin 26. |
| 10 | A3 | addr | Address bus bit 3. Direction not stated in the cited pin figures. UNVERIFIED |
| 11 | A2 | addr | Address bus bit 2. Direction not stated in the cited pin figures. UNVERIFIED |
| 12 | A1 | addr | Address bus bit 1. Direction not stated in the cited pin figures. UNVERIFIED |
| 13 | A0 | addr | Address bus bit 0. Direction not stated in the cited pin figures. UNVERIFIED |
| 14 | R/W | ctrl | Read or write. Direction not stated in the cited pin figures. UNVERIFIED |
| 15 | RDY | ctrl | Ready output to the CPU RDY pin. LOW holds the CPU. |
| 16 | A10 | addr | Address bus bit 10. Direction not stated in the cited pin figures. UNVERIFIED |
| 17 | A12 | addr | Address bus bit 12. Direction not stated in the cited pin figures. UNVERIFIED |
| 18 | A13 | addr | Address bus bit 13. Direction not stated in the cited pin figures. UNVERIFIED |
| 19 | A14 | addr | Address bus bit 14. Direction not stated in the cited pin figures. UNVERIFIED |
| 20 | A15 | addr | Address bus bit 15. Direction not stated in the cited pin figures. UNVERIFIED |
| 21 | Vdd | power | +5 V supply. |
| 22 | A11 | addr | Address bus bit 11. Direction not stated in the cited pin figures. UNVERIFIED |
| 23 | A9 | addr | Address bus bit 9. Direction not stated in the cited pin figures. UNVERIFIED |
| 24 | A8 | addr | Address bus bit 8. Direction not stated in the cited pin figures. UNVERIFIED |
| 25 | A7 | addr | Address bus bit 7. Direction not stated in the cited pin figures. UNVERIFIED |
| 26 | A6 | addr | Address bus bit 6. Direction not stated in the cited pin figures. UNVERIFIED |
| 27 | A5 | addr | Address bus bit 5. Direction not stated in the cited pin figures. UNVERIFIED |
| 28 | A4 | addr | Address bus bit 4. Direction not stated in the cited pin figures. UNVERIFIED |
| 29 | PHI2 | clock | Phase 2 clock in, from the CPU. |
| 30 | D0 | data | Data bus bit 0. |
| 31 | D1 | data | Data bus bit 1. |
| 32 | D2 | data | Data bus bit 2. |
| 33 | D3 | data | Data bus bit 3. |
| 34 | PHI0 | clock | Phase 0 clock out to the CPU PHI0 input (pin 37). |
| 35 | FPHI0 | clock | Fast phase 0 clock in, from GTIA pin 29. ANTIC divides it by two for PHI0 (pin 34). |
| 36 | /RST | ctrl | Reset. LOW resets ANTIC at power-up. |
| 37 | D7 | data | Data bus bit 7. |
| 38 | D6 | data | Data bus bit 6. |
| 39 | D5 | data | Data bus bit 5. |
| 40 | D4 | data | Data bus bit 4. |
Fitted in
- Atari 400 A302 (CPU board)
- Atari 800 A302 (CPU board)
- Atari 600XL U9
- Atari 800XL U7
- Atari 130XE U7